Our next #YUG will be with Matt Young, talking about triple modular redundancy.
Join us at 18:00 CET / 22:30 IST / 09:00 PT on Thursday 9th October.
Sign up to our mailing list to get a reminder before the event: blog.yosyshq.com/newsletter/
I will work on exploring applications of Aristotle to the formal verification of hardware. This job is a perfect intersection of hardware design and verification, functional programming, formal methods and machine learning, bringing together several threads of my career so far.
"High-Level Synthesis Synthesis"
stefanabikaram.com/writing/hls-...
Some fun writing on hardware design pedantry
[New Blog Post] Proving the Infinitude of Primes in Knuckledragger #python #logic www.philipzucker.com/knuckle_prim...
i built a pages server for Codeberg that's way cheaper to operate than the existing one, please enjoy grebedoc.dev/
I got inspired at orconf, so now play.spade-lang.org supports a full in-browser flow for submitting to tinytapeout.com/
Still experimental, so if you try it and run into any issues, let me know :)
A lovely Xilinx 7-series FPGA chip layout of a sorting network produced from a dependently typed DSL in Haskell. More stuff like this during my keynote talk at ICFP 2025 in October in Singapore. icfp25.sigplan.org/details/icfp...
I did some more hacking to produce a totally floorplanned 64-input sorter circuit on a Xilinx XC7A200T FPGA, on the LHS picture shown as a tight rectangular block, on the RHS a close-up that shows the butterfly wiring pattern.
Check out the fantastic open source hardware hacker content from this weekend’s ORCONF’25!
fossi-foundation.org/orconf/2025?...
HT/thanks @mattvenn.net
Shout out to all the CGRA folks, all jokes are in good fun
new preprint, tl;dr:
• LLMs match or exceed SOTA strategies on chemical reaction optimizations.
• we built the Iron Mind platform and we hope that it can serve as a new benchmark for both reaction optimizers and foundation models.
a thread [1/5]
Lindsey Kuper's* group has produced this fantastic zine on choreographic programming that folks should definitely check out: decomposition.al/blog/2024/12...
(* can't seem to find Lindsey here but please tag if you know the handle)
Today at ASPLOS Chengsong Tan will present our work with @wicko3.bsky.social on mechanical formalisation of CXL.cache - check out the paper! www.doc.ic.ac.uk/~afd/papers/... #CXL
This study of deep learning optimizers found that previously claimed speedups of alternative optimizers over AdamW in language model pretraining were often inflated due to methodological shortcomings like unequal hyperparameter tuning and limited evaluation.
Benchmarking the variety of different proposed LLM optimizers: Muon, AdEMAMix, ... all in the same setting, tuned, with varying model size, batch size, and training duration!
They find that AdEMAMix is SOTA, the importance of weight decay, or how Muon “prefers” WSD, and more...
Paper: Benchmarking Optimizers for Large Language Model Pretraining
( arxiv.org/abs/2509.01440 )
Repo: github.com/epfml/llm-op...
I have yet to read “Computer Architecture: A Quantitative Approach”
The internal operating system of the Fujitsu FM TOWNS computer. A few windows are open; one shows the disk drives and one shows the contents of the physical CD-ROM inserted into it.
We were cooked the moment operating system UIs stopped shipping looking like this
Lakritz FPGA dev board driving widescreen monitor showing picture of purple and white crocuses. The monitor is running at 1366x768.
Over the weekend I released the next part of Isle #FPGA Computer covering bitmap graphics.
projectf.io/isle/bitmap-...
I've added more docs and tests, but I'm still finding the right approach to the Isle blog and working on diagrams.
This Friday I successfully defended my PhD 🎉 If you want to watch a recording of the defense there is a recording here vimeo.com/1114208379/89dcd4f302
Then and now, Prof. Cong and students trailblaze new design automation research for mainstream high level synthesis tools and myriad applications.
Chuck Thacker made beautiful computers with FPGAs, so this award seems particularly apt.
web.mit.edu/6.173/www/cu...
www.cl.cam.ac.uk/~swm11/examp...
arxiv 📄 Evaluating Large Language Models for Automatic Register Transfer Logic
Generation via High-Level Synthesis
http://arxiv.org/abs/2408.02793v1
The ever-growing popularity of large language models (LLMs) has resulted in
their increasing adoption for hardware design and verification. Prio...
Zedong Peng, Zeju Li, Mingzhe Gao, Qiang Xu, Chen Zhang, Jieru Zhao: ForgeHLS: A Large-Scale, Open-Source Dataset for High-Level Synthesis https://arxiv.org/abs/2507.03255 https://arxiv.org/pdf/2507.03255 https://arxiv.org/html/2507.03255
Huge congrats to Yann Herklotz (@ymherklotz) for successfully defending his PhD thesis today, all about his proven-in-Coq high-level synthesis tool. And enormous thanks to George Constantinides (@gconstantinides) and Xavier Leroy for their thoughtful and thorough examining.
Here is a short blog post about an #FCCM2021 paper that will be presented next week by @ymherklotz about our work (with Zewei Du and @nadeshr5) on finding bugs in high-level synthesis tools using #fuzzing. johnwickerson.wordpress.com/2021/05/07/fuzzing-hls/
Martin Langhammer, George A. Constantinides: Banked Memories for Soft SIMT Processors https://arxiv.org/abs/2503.24132 https://arxiv.org/pdf/2503.24132 https://arxiv.org/html/2503.24132
I can't* fathom why the top picture, and not the bottom picture, is the standard diagram for an autoencoder.
The whole idea of an autoencoder is that you complete a round trip and seek cycle consistency—why lay out the network linearly?
"On the Theoretical Limitations of Embedding-based Retrieval"
Paper: arxiv.org/abs/2508.21038
Repo: github.com/google-deepm...
Rishov Sarkar, Cong Hao: OmniSim: Simulating Hardware with C Speed and RTL Accuracy for High-Level Synthesis Designs https://arxiv.org/abs/2508.19299 https://arxiv.org/pdf/2508.19299 https://arxiv.org/html/2508.19299
