Want to play? 😋

Made with verilog.

So this one guy submitted a very cool entry for @tinytapeout.com's demoscene competition.

I really liked the gradient and banner and whole starry sky implemented with LFSR.

It's crazy that we can put all of this in one or two tiles.

cooking an asic for demoscene competition 🤘

@tinytapeout.com

it'll make asics!

The real question is that where do you draw the line on democratizing silicon?

These are bare dies of the Kintex-7 XC7K325T and its pin-compatible Chinese clone, the JFM7K325T from Fudan Micro.

Only difference is that GTX transceivers of JFM7K325T behave differently, so the xilinx pcie core wouldn't work by default.

I was just reading this!! ✨

sit down mehdi....

sometime back there was a whole online mob by same set of people who tried to attack hindus merely for existing in america.

ANTHROPIC !!!! 👏👏

BREAKING

TRUMP ANNOUNCES MAGAS WILL BECOME 10% MORE STUPID & BELOW THE AVERAGE IQ.

Fly through video for ROM-less Cordic Engine design.

This design is on TTSKY25A shuttle by @tinytapeout.com

Made easy with BlenderGDS plugin - github.com/aesc-silicon...

@mattvenn.net @urishaked.bsky.social @aksharvastarpara.bsky.social

Fly through video for ROM-less Cordic Engine design.

This design is on TTSKY25A shuttle by @tinytapeout.com

Made easy with BlenderGDS plugin - github.com/aesc-silicon...

@mattvenn.net @urishaked.bsky.social @aksharvastarpara.bsky.social

How well do SP10 probes perform when used with high-frequency oscilloscope measurements?

welcome to our cordic city!!

welcome to our cordic city!!

yes! it's from that same blender plugin.

Yes, that’s a GDSII render.
Yes, it’s inside Blender.
Yes, it’s our design on TTSKY25A chip.
@tinytapeout.com @mattvenn.net @urishaked.bsky.social

oh! got it.

can you post the "GPU running on FPGA"?

....while CSIS sponsers terrorism on Indian soil.

Innovation in ZMOS process node led to development of modern CMOS and BiCMOS process node where we have 20 metal layers.

For instance, Sky130A 130nm process node have upto 5 metal layers.
bsky.app/profile/roha...

Back in the day, NMOS chips used only one metal layer, so designers had to squeeze all the wiring onto a single surface.

Metal 1: used for local interconnects, this allowed short and dense wiring.

Metal 2: used for global signals like buses, clocks, power.

This is the DCJ11 PDP-11 processor, built using the old-school ZMOS tech, a 3  μm NMOS process with two interconnect layers.

It was one of the first NMOS processes to use separate metal layers for local connections and global signals.

🤩🤩

Another mike bell project to fab!

Fomu fpga?

chinese semiconductor industry is creative for sure.

Nice idea for analog tapeout for some day.

This looks like a matrix.
Each one has 128 analog switches.
We can do 8x16 analog array with one.

So this is actually a analog matrix.

And guess what whole hdl for this is written in both system verilog and chisel/scala.

Note that Zve32x extension works only on integers, it needs Zicsr and Zvl32b base profiles to be implemented first.

Although the element size is capped at 32 bits, the wide vector registers (256 bits) still allow multiple elements to be processed simultaneously.

Google has open sourced its Coral NPU, which uses a 32 bit RISC V core with the Zve32x extension. It supports vector arithmetic on data ≤ 32 bits, making it great for DSP applications.

It has been prototyped on a Xilinx Ultrascale Plus FPGA platform.

github.com/google-coral...