ASIC plugged into a monitor showing the Trans flag

Happy Trans day of visibility from a Tiny Tapeout ASIC!

Join us in just over 3 hours for our 12th Yosys User's Group!

Sign up to our mailing list to get a reminder before the event: blog.yosyshq.com/newsletter/

Join the meeting here: meet.jit.si/yosys-users-...

For our 12th Yosys User’s Group we’re inviting your questions! What have you always wanted to ask the team?

- Formal verification
- Synthesis
- Plugins / internals
- How to contribute
- Roadmap

Join us at 18:00 CET / 22:30 IST / 09:00 PT on Thursday 12th February.

Simulating RF Reality: VNAs, OpenEMS, and an On-Chip Antenna Design with Ghaith YouTube video by Zero To ASIC Course

At RF, your circuit stops being “small” compared to the signal - and everything changes.

New video interview about RF design, VNAs, simulation, and on-chip antennas.

www.youtube.com/watch?v=2xSA...

The last month of my life: BreakingTTAPs

This is a custom transport-triggered, 32 bit processor that will be fabricated by GlobalFoundries on their 180nm process (via of wafer.space)

I'll make a video at some point, but some high level details here:

What open source ASIC tools am I excited by in 2025? OpenEMS, 3D viewers, Surfer, OpenROAD, and lots more!

Check this article for all the links: zerotoasiccourse.com/post/excited...

#opensource #ASIC #tools

Formal Verification Adoption Made Easy - DVWorld Club YouTube video by YosysHQ

Ever wanted to try adding formal verification to your project but it seemed too hard or expensive to get started? In this video @mattvenn.net Venn shows you an easy way to get up and running with our open source tools and GitHub actions!

youtu.be/Tn5wCOhzfvs

#Verification #Formal #OpenSource

Tiny Tapeout - Tiny Tapeout From idea to chip design in minutes! Tiny Tapeout is an educational project that makes it easier and cheaper than ever to get your designs manufactured on a real chip.

You have just 10 days left to get your #ASIC design submitted to our TTSKY25b shuttle!

There are still 70 early bird dev kits left, which mean you can do a full custom tapeout for just €185!

Get started here: tinytapeout.com

Starting in just over an hour!
meet.jit.si/yosys-users-...

Join us tomorrow at 18:00 CEST!

this is me!! very much looking forward to presenting :3 please come join if you're interested in spaceflight/fault-tolerant computing or EDA algorithms! #yosys #eda

Our next #YUG will be with Matt Young, talking about triple modular redundancy.

Join us at 18:00 CET / 22:30 IST / 09:00 PT on Thursday 9th October.

Sign up to our mailing list to get a reminder before the event: blog.yosyshq.com/newsletter/

Title slide: "adventures with FPGAs", with a composite background made of photos of FPGAs and peripherals

Teaching processor design at Telecom Nancy
Lesson 1: build your own risc-V processor at home using a FPGA
Course notes are here:
github.com/BrunoLevy/le...

Jobs Employee Profile: Synthesis or Formal Verification Developer at YosysHQ You might know YosysHQ from our many Open Source EDA Projects. We are the maintainers of Yosys and the accompanying Open Source ...

We are hiring! Both technical and admin, please take a look at our jobs page!

www.yosyshq.com/jobs

#jobs #hire

TaMaRa: Towards a Triple Modular Redundancy Pass for Yosys This is a guest blog post by Matt Young\n# Foreword Although I’m a computer scientist by education, I’ve always been interested in space since I was a kid. For a long time, I had simply forgotten abou...

In our latest guest blog post, Matt Young introduces an Automated Triple Modular Redundancy EDA Flow for Yosys!

blog.yosyshq.com/p/tamara-tow...

A coconut sapling on a tropical beach.

Isle 🏝️ is my new #FPGA project.

Isle is a simple, modern computer — an open design that encourages tinkering, experimentation, and doing your own thing. I hope to inspire you to come on a journey with me and build your own computer. projectf.io/isle/fpga-co...

Want to help build a crowdsourced microcontroller?

You're invited to design peripherals (UARTs, timers, synths, etc.) for a @riscv.org.web.brid.gy chip that will be fabbed for real!

Take part for free!

tinytapeout.com/competitions...

We have a new home for community discussion around Yosys

yosyshq.discourse.group

Join us there for questions, support and discussion about our open source EDA tools.

#community #opensource #Yosys

We have a new home for community discussion around Yosys

yosyshq.discourse.group

Join us there for questions, support and discussion about our open source EDA tools.

#community #opensource #Yosys

Yes, if yosys and friends didn't exist I probably wouldn't have done any HW side projects, so i'd never have started Spade or Surfer

My thesis is now published online! 🎉

urn.kb.se/resolve?urn=...

IHP25b - our 4th open source chip with IHP is now open for digital design submissions!

We’re very happy to have our next shuttle open and we’re already looking forward to seeing another great set of designs manufactured onto custom silicon!

We’re close to making key decisions about future shuttles—and we want your input! 💬

What features matter most? What’s your price ceiling?

Take our 2-min survey 👉 forms.gle/EMrSJQ6dmw4P...

🎁 One respondent will win a beautiful 150mm silicon wafer!

Bad AAPL

Release nextpnr 0.8 · YosysHQ/nextpnr Remove nextpnr-gowin; replaced by Gowin support in nextpnr-himbaechel Remove unmaintained FPGA interchange support Updated and reworked CMake build system Himbaechel: Numerous improvements to Gowin...

Good news open-source #FPGA fans, there's a new release of nextpnr (place and route) from @yosyshq.com. The release notes mention "Numerous improvements to Gowin support": github.com/YosysHQ/next...

Join us in a few hours for a talk about ASIC synthesis with Yosys!

18:00 CET / 22:30 IST / 09:00 PT

meet.jit.si/yosys-users-...

Emil will be covering:

* ASIC synthesis in general
* Yosys scripts
* abc scripts
* New Yosys features for ASIC

Join us at 18:00 CET / 22:30 IST / 09:00 PT on Thursday 20th.

Sign up to our mailing list to get a reminder before the event: blog.yosyshq.com/newsletter/

It's time for another YUG! What's a YUG? It's the Yosys User's Group! For anyone interested in using Yosys - we've had sessions on primitives, plugins, hardware security, FPGAs and lots more...

This time we'll be turning to #ASIC synthesis with our own Emil Jiří Tywoniak.

Simulation Simulation is the ASIC terminology of the week!

Simulation is the #ASIC terminology of the week!
In the last month, Simulation has been the 35th most popular out of 42 terms.