Introducing Ricursive Intelligence, a frontier AI lab enabling a recursive self-improvement loop between AI and the chips that fuel it.
#chip_design #ai #eat_your_own_dog_food #ricursive
www.ricursive.com
Lean Together online conference: 19—23 Jan 2026:
Lean Together is an annual meeting for users, developers, and fans of the Lean programming language and theorem proverand its library Mathlib maintained by the Lean Community.
#LeanLang #LeanProver
leanprover-community.github.io/lt2026/
The Lean FRO ‘Year 3’ (August 2025 - July 2026) Roadmap - released today:
lean-lang.org/fro/roadmap/...
#LeanLang #roadmap #high_performance_verification #proof_automation
#FPGA #RISCV
2GRVI Phalanx at Hot Chips 31: The First Kilocore RISC-V RV64I with HBM2 High Bandwidth Memory
fpga.org/2019/08/19/2...
How to contribute…
Attended Leo de Moura’s talk about @leanprover at #CADE_30 in Stuttgart/Germany. Lot’s of stuff in the pipeline! And whether it’s #Agda or #lean_lang I want to learn more about dependent types, proofs and how to apply them in my daily work!
The slides: leodemoura.github.io/files/CADE25...
#JFS2025: Wie kann ich Java schneller starten – und wann lohnt sich das?
Schneller starten, weniger Ressourcen verschwenden: Von einfachem Tuning bis zu GraalVM Native Image gibt es viele Wege, Java-Anwendungen auf Tempo zu bringen.
www.java-forum-stuttgart.de/vortraege/wi...
#FPGA “With “A3CZ135BB18AE7S,
Largest Agilex 3 FPGA with 135K logic elements”.
Seems like a fine, modern hobbyist platform.
$169 per www.terasic.com.tw/cgi-bin/page...
The famous ‚Die Hard‘ problem with GenAI-accelerated TLAi+ by Markus Kuppe (now with NVIDIA):
youtu.be/JX_kTGHoYT8
#tlaplus #executableSpecification
Yay! My Inspur XC7K480T FPGA development Board acceleration Card YPCB-00338-1P1 arrived!
#FPGA #Kintex #RISCV #openXC7
From Luca Benini
The letter for support of open chip fabrication access for EU students, AKA *Democratizing silicon* for EU promoted by @pulp_platform and many others has already more than 300 signatories. We can do better, though. Please sign if you agree open-source-chips.eu
#open_source #chips
Sam Altman:
…. we have greatly improved memory in chatgpt--it can now reference all your past conversations!
this is a surprisingly great feature imo, and it points at something we are excited about: AI SYSTEMS THAT GET TO KNOW YOU OVER YOUR LIFE, and become extremely useful and personalized.
👀
LLM-accelerated TLA+? A proposal from #MarkusKuppe to develop MCP integration for TLA+ tools…Let’s see if this will be implemented in the near future! 😎
github.com/tlaplus/founda…
#TLAPlus #MarkusKuppe #TemporalLogic #ModelChecking #LLM #FormalVerification
The Joy of Hardware Manifesto 🚀
joyofhardware.com
…Our in-browser IDE will let you write, compile, and program hardware without ever leaving your browser.
#FPGA #Bluespec #Nix
Engineers@Work! Decisions made by engineers to keep Mars Ingenuity (the helicopter 🚁) running! Or, you should be able to patch your system anytime! 😎
youtu.be/20vUNgRdB4o
#JPL #Mars #Ingenuity #ProblemSolving
Attempto Controlled English (ACE) is knowledge representation, specification, and a query language. For experts who want to use formal notations and formal methods, but may not be familiar with them.
#software_specifiation #ontology #proof_assistants
attempto.ifi.uzh.ch/site/
End-to-end vendor-neutral formal verification solution for RISC-V
youtu.be/V8n_-zz8SG0
#riscv #formalVerification #formalISA
Visualizing WiFi signals in a really cool way:
youtu.be/sXwDrcd1t-E
#ESP32 #wifi #visualize
#RISC-V Composable Extensions: The Extension Logic Interface *Workshop* with #RoCC, #CV_X_IF, #SCAIE_V and #CXU_LI presented as RISC-V extensions:
youtu.be/YtdVpkCIXtE
PULP Platform: Frank's slides presented yesterday at the First TAICHIP Winter School in Frankfurt an der Oder are now online. Find "PULP and AI Acceleration" here: pulp-platform.org/docs/taichip...
#AI #Acceleration #EnergyChallange
The Call For Papers (CFP) for the Java Forum Stuttgart 2025 started:
java-forum-stuttgart.de/cfp-anmeldung/
#Java #Kotlin #AI #JavaForumStuttgart
DeepSeek is a Game Changer for AI - Computerphile: youtu.be/gY4Z-9QlZ64
☕️ We’re running LATTE again: our ASPLOS workshop about languages/compilers/tools/whatever for hardware design.
Submissions are just little 2-pagers, due on January 31. Plenty of time to throw something together! capra.cs.cornell.edu/latte25/
…Ubitium’s RISC-V processor sounds like an FPGA, ... But while FPGAs tend to come short of chips designed for specific uses in areas like performance, efficiency, and value, Ubititum says the Universal Processor will be “smaller, more energy-efficient, and significantly less costly.”
