Intel Announces Retirement of CEO Pat Gelsinger

Intel CEO Pat Gelsinger retiring effective today. www.intc.com/news-events/...

Lego set of a ASML lithography machine

Looking for a Christmas gift? There's a Lego set of a asml EUV machine 😍

This is pretty interesting

This is the first time I'm seeing this direct contact style of mask printing. It's very different, I'm wondering what the reticle size is and what size wafers they can fab? #semiconductors

A photograph of woven tapestry of the silicon chip layout of a MOS 6502 microprocessor, enlarged to approximately 1.8 metres wide and 1.2 metres high hanging on a wall in a golden frame.

My most interesting contribution to computing is perhaps this woven tapestry of a MOS 6502 microprocessor which I commissioned and for which I built the golden frame. It’s almost two metres wide and hangs on the wall in a colleague’s office to improve the acoustics.

Episode 94: Chatting Apple Silicon with Apple's Tim Millet and Tom Boger | The Circuit | Episode 94

Interesting discussion on 'The Circuit' about Apple Silicon and the role of performance per watt with Tom Boger and Tim Millet

share.transistor.fm/s/124f8bc4

EUV is pretty power consuming

Engineering the Gate-All-Around Transistor YouTube video by Applied Materials

Amazing explanation by applied materials how a GAA #transistor is fabricated

www.youtube.com/watch?v=xaKy...

The photomask defines the pattern which should get transferred onto the chip. With this process nodes <10nm can be manufactured without using advanced techniques like multipatterning. This allows increasing the throughput compared to #DUV making it cost efficient.

These mirrors have multiple only nm-thick layers of Si and Mo achieving a reflectivity of ~70%. The mirrors produced by #Zeiss must be extremely precise and are one of the most expensive parts in the tool. The mirrors bundle and align the EUV light which then hits the #photomask.

As light source a tin droplet with a diameter of 30 micron is hit by a CO2 laser pulse generating a plasma. This plasma emits EUV light with a wavelength of 13.5nm. Since EUV light is absorbed by most materials including conventional lenses, the optics in the tool is entirely based on mirrors.

The picture shows an ASML lighography tool of the size 10x4x4 meters. It is a schematic with the main focus on a complicated projection optic. A from an EUV light source a beam hits a photo mask via multiple lenses and mirrors. From the mask the pattern is transferred to a wafer which is placed on a stage. This projection optic is embedded in a vacuum chamber and surrounded by lots of wiring.

Today I want to present to you the in my opinion most impressive machine in the world: The #EUV (extreme ultraviolet) #lithography tool of #ASML. The tool has a size of 10x4x4 meters and costs ~200 million Euros. This tool is used for the fabrication of every modern chip in the world.

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single blocks as cache, memory, etc. These blocks can be optimized separately and by an advanced BEOL stacked to a 3D chip. More of the concept of CMOS2.0 will be presented here in future.

of the CEFT design will be handling of the interconnects. Therefore the scaling roadmap additionally includes an interconnect roadmap. Major design adaption will be needed, e.g. backside power supply. This leads to the concept of #CMOS2.0. The main idea is a redesign of the full SOC, by optimizing

GAA devices will be potentially be superseded by Forksheet FETs (FSFET) or in other versions of the roadmap directly by complementary FETs (CFET). These geometries are not in detail defined yet, the main idea of a CEFT is to stack a nMOS and a pMOS device allowing further scaling. One main challenge

While in finFETs the gate wraps around the semicond. channel on three sides (forming a fin), in GAA devices the gate surrounds the channel completely. This leads to a better electrostatic control and reduces short-channel effects which allows further scaling.

Chart with the title "Potential logic scaling roadmap extension" presented by imec. The chart is split into 4 rows and shows a timefline from 2018 to 2036. the rows show the name of the node, the metal pitch in nanometer, the name of the used MOSFET and an schematic of a context-aware interconnect. 2018: N7, 40nm, finFET 2020: N5, 28nm, finFET 2022: N3, 21nm, finFET 2024: N2, 21nm, GAA NSFET 2026: A14, 28nm, GAANSFET 2028: A10, 18nm, FSFET 2030: A7, 16nm, FSFET 2032: A5, 16nm, CFET (with 4 complementary FETs) 2034: A3, 16nm, CFET (with 8 complementary FETs) 2036: A2, 16-12nm, CFET atomic

Today I want to present to you the potential scaling roadmap for transistors presented by #imec. While finFETs have been dominating logic in the last couple of years, #Samsung and #TSMC have shifted to Gate-All-Around (GAA) devices which will dominate the market in the next years.

I already pinned it, thanks a lot :)

(PDF) Global Semiconductor Trends and the Future of EU Chip Capabilities PDF | The proposed European chips act, presented by the European Commission in February 2022, aims to mobilise €43 billion in 'policy-driven investment'... | Find, read and cite all the research you n...

Figures in this thread are take from the paper "Global Semiconductor Trends and the Future of EU Chip Capabilities" by Kjeld van Wieringen.
www.researchgate.net/publication/...

What is the future bringing for Europe? The European Chips Act aims to mobilize 43 Billion Euros. Modern foundries are build by Intel and TSMC in Germany. Research is booming. Exciting times are coming.

Chart which shows Market shares of various Fields: RnD: 60% US 6% Europe <10nm Node: 92% Taiwan, 8% South Korea 10-22nm Node: 43%US, 12% Europe, 28% Taiwan Euipment: 41%US 18% Europe, 32% Japan Wafers: 14% Europe, 16% Taiwan, 56% Japan Foundries: 10%US, 9%China, 60%Taiwan 19% South Korea, 2% Rest of world Total value chain: 38% US, 9% China, 10%Europe, 9% Taiwan, 16% South Corea, 14% Japan

While many of these foundries are quite successful in their specialized field, they play a minor role in the global semiconductor market. Market shares show clearly that the only European presence is in manufacturing equipment (dominated by ASML) and older nodes.

There are multiple state-of-the-art chip foundries specialized in various technologies like power devices for automotive/solar (Infineon), MEMS (Bosch), etc. but none of these foundries builds modern logic for CPUs or GPUs.

The by far most important Europ. player is #ASML. ASLM is the only manufacturer capable of building EUV lithography tools which are needed for building every single modern chip. These lithography tools are mainly shipped to Taiwan and South Korea, where the majority of high-end nodes are fabricated.

There are three important research centers: #imec (Belgium), #CEA-Leti (France) and #Fraunhofer (Germany). Especially imec is extremely prestigious and probably the most important semiconductor research institution in the world. Research done by imec will be future content of this account.

Map of Europe which shows the most important Research centers, Quipment manufacturers, Chip foundries, Chemical industries and Wafer manufacturers. ASML - Equipment - Netherlands NXP - Chip foundry - Netherlands imec - Research - Belgium Nexperia - Chip foundry - Netherlands Melexis - Chip foundry BASF - Chemicals - Germany Intel - Chip foundry - Germany x-FAB - Chip foundry - Germany Zeiss - Equipment - Germany Bosch - Chip foundry - Germany AMS - Chip foundry - Austria Infineon - Chip foundry - Germany/Austria Fraunhofer - Research - Germany Glofe - Wafers - Germany CEA-Leit - Research - France STM - Foundry - Switzerland/France/Italy Bosch - Foundry - Germany

In my first thread I would like to give you an overview of the European semiconductor business.

I noticed that there is a lack of #semiconductor content on bluesky. Since we hate twitter but love semiconductors, it is time to contribute some chip content