Rubin CPX looks very similar to GB202, at least in the image Nvidia released. Could be very well a full GPU, with raster engines, PCI-Expess and display outputs. While unlikely, it might be how the RTX 6090 will look like.
#Intel #GraniteRapids SKU stack:
cdrdv2-public.intel.com/860027/Intel...
Intel's newer Emerald Rapids improves L3 latency compared to Sapphire Rapids, at least when one core is able to allocate a similar amount of L3 capacity. It's still high at ~105 core cycles, but better than ~125 cycles from the last generation.
Fake website servic welcome page. text reads: "Your favorite tool is now ruined by AI" "you might not like it but shareholders love it"
when you open a service you've been using for a decade only to find it out it caught the virus
oh and fuck Future, PLC. they are the ones that killed AnandTech as well.
my NGJ2025 talk about Quaternions is up! 💫
www.youtube.com/watch?v=PMvI...
AMD Navi 44 GPU
- 29.7 Billion Transistors
- 199 mm² Die Size
An Intel slide with #NovaLakeU, #NovaLakeS, #WildcatLake, P-Only #BartlettLake:
www.intel.com/content/www/...
Just released by @fritzchensfritz.bsky.social
Arrow Lake-S die shots projected on the full package.
Full resolution: www.flickr.com/photos/13056...
this isn't clickbait, watch it before nintendo gets it taken down lol www.youtube.com/watch?v=3pr_...
Venice Classic SP8 → 8 CCD * 12 = 96 cores
Venice Dense SP7 → 8 CCD * 32 = 256 cores
?
🤔
Could more closely mirror Intel's 2 platform strategy, especially if SP8 supports 2P configurations
It seems there will be #AM5 #AMD #GorgonPoint as well
docs.amd.com/search/all?c...
Soon™ 🏹🌊👀
AMD had a separate Shader Array subdivision within Shader Engines even in the original GCN architecture. Interesting that it never mattered until RDNA added a L1 cache to the Shader Arrays and had multiple SAs per SE
I recently had the honor of interviewing Zen’s chief architect Mike Clark! I tried to fit in as many microarchitecture questions as I could, including x64 vs ARM ISA power efficiency, 4k vs larger page sizes, 64-byte cache lines, scatter/gather and more:
www.computerenhance.com/p/an-intervi...
Good news: according to ark.intel.com, every #Intel #GraniteRapids-based #Xeon6 6900P, 6700P, 6500P SKU supports #AVX512 with dual 512bFMA, even the #GraniteRidgeD ones too
www.intel.com/content/www/...
Re: Nova Lake rumors
In before 8P16E dies get canned in favour of double 4P8E or 6P8E compute tiles for Nova Lake-S
I just can't take 2x8P16E at face value after the cancellation of 8P32E Arrow Lake
It's not like a 12P16E4e flagship with Big LLC would be *that* uncompetitive with Medusa, right?
Does anyone know why Apple did not release any chip pictures / die shots for the M4 series, like they usually do? I know there's a @techinsightsinc.bsky.social M4 die shot floating around, but I always enjoyed the images Apple released directly. Maybe someone has contacts at Apple?
Visualizing the massive size difference between AMD's Zen 5 CCD & Nvidia's GB202.
Here's a quick look at Nvidia's GB203, image from "ASUS Tony". Spec wise basically 1/2 GB202, but physically a different design and not just half of a GB202.
Is the fact that Samsung is only using the Snapdragon 8 Elite for the Galaxy S25 series a sign of strength for Qualcomm or a sign of weakness for Samsung's SoC team and Foundry? Or does it just not matter?
Transistor count and die size for GB202, GB203 and GB205 aka Blackwell. Those and the predecessors are all manufactured in TSMC 4N.
Source: www.hardwareluxx.de/index.php/ar...
"380 Ray tracing TFLOPS" will be on the list of things that drive me to be committed
Is GB10 the high-end NVIDIA Laptop SoC?
Because otherwise why would it have an asymmetric CPU layout?
Looks like 2 clusters with 5x Cortex-X + 5x Cortex-A each
It also seems to have all the I/O you'd want for a Laptop
"1000 FP4 TOPS" (24TPCs?) would correspond GB205 (5070Ti Laptop) performance
In this paper is presented the Nanoscaling Floating-Point, a set of three techniques to enable better accuracy and smaller memory footprint than state-of- the-art microscaling standard floating-point.
arxiv.org/pdf/2412.19821
Has anyone been able to find the actual document? There’s no link in the article, no link in the press release, no document in their white paper or documentation section on their site…
Even the performance optimization manual is vaporware??
I wonder if the bigger Battlemage die (BMG-G31) could use this same package. There seems to be a lot of leftover space at the top-right, and package reuse would also mirror NVIDIA's strategy of having AD104 and AD103 share packages
Why Hybrid Bonding is the Future of Packaging
youtu.be/OlRLuajAgIc
I expect the Arc B580 to be around the A770 in performance, but have lower power consumption (somewhat closer to eg. 7600), as that would match the improvements we've seen with AMD going from N7- to N5-class nodes
That would still be terrible PPAC vs the competition though, so I'd hope for more
