#3DHI

Call for Papers: IEEE JXCDC
Submit original works on physical realizations, cross-layer modeling & thermal-aware co-design to advance energy-efficient AI via 3D Heterogeneous Integration beyond planar limits.

📅 Deadline: May 15, 2026 🔗 https://bit.ly/3LZez8e

#AI #3DHI #IEEE

Call for Papers: IEEE JXCDC
Submit original works on physical realizations, cross-layer modeling & thermal-aware co-design to advance energy-efficient AI via 3D Heterogeneous Integration beyond planar limits.

📅 Deadline: May 15, 2026 🔗 https://bit.ly/3LZez8e

#AI #3DHI #IEEE

Call for Papers: IEEE JXCDC
Submit original works on physical realizations, cross-layer modeling & thermal-aware co-design to advance energy-efficient AI via 3D Heterogeneous Integration beyond planar limits.

📅 Deadline: May 15, 2026 🔗 https://bit.ly/3LZez8e

#AI #3DHI #IEEE

Why Is DARPA Betting on 3D Heterogeneous Integration? Can a 1980s-era fab in Austin transform the future of microelectronics with 3D heterogeneous integration?

"A 1980s-era semiconductor fab in #Austin, Texas, is getting a makeover."

Today's #electronics lunchtime read: @spectrum.ieee.org's Samuel Moore visited a new, @darpa.mil semiconductor facility that is dedicated to the production & packaging of stacked chips (both silicon & non-)! #3DHI