Official #Intel #WildCatLake SKU list:
www.intel.com/content/www/...

#VisualStudio2026 Insider implements the #AVX512_BMM instructions
#AMD #Zen6

#AMD refreshed the "AMD I/O Virtualization Technology (IOMMU) Specification" to 3.11:
docs.amd.com/v/u/en-US/48...

GitHub:
github.com/InstLatx64/I...

#Intel re-released the 91st edition of the Software Developer’s Manuals with minor fixes:
cdrdv2-public.intel.com/916575/32546...

#Intel released the 91st edition of the Software Developer’s Manuals with canonized #AMX_COMPLEX.
All-in-One:
cdrdv2-public.intel.com/916575/32546...
Changes v83:
cdrdv2-public.intel.com/916574/25204...

#AMD released the 12th #Zen6 pdf "AMD64 Zen6 Platform Quality of Service (PQOS) Extensions" 69193 v1.00:
docs.amd.com/v/u/en-US/69...
CPUID 80000020h.EBX:
b[7] = Global Bandwidth Enforcement (GLBE)
b[8] = Global Slow Bandwidth Enforcement (GLSBE)
b[9] = Privilege Level Zero Association (PLZA)

My quick note about #Intel
#BartlettLake CPUID D0670
and
#RaptorLake CPUID B0671 #RaptorCove
instruction level differences

New #Intel dumps:
-- 12P+0E #Intel Core 9 273PQE #BartlettLake D0670
GitHub:
github.com/InstLatx64/I...
github.com/InstLatx64/I...

#AMD released the 11th #Zen6 pdf "AMD64 Enhanced SMT Protection" 69204 v1.00:
docs.amd.com/v/u/en-US/69...
CPUID Fn8000_00025_EDX[1] = EnhSmtProtection

This is currently the only document assigned to #Sorano on the #AMD website:

#Intel released the SDE 10.8 (Software Development Emulator):
www.intel.com/content/www/...
#NovaLake #DiamondRapids #APX #AVX10_2

#Intel refreshed the "Intel XMP 3.0 Memory for Intel Core™ Processors Datasheet" xls with #ArrowLake Plus:
www.intel.com/content/www/...

#Intel released the 61st edition of the ISA Extensions Reference with PerfMon Masking and clarifications.
Download:
cdrdv2-public.intel.com/915637/31943...
#DiamondRapids #NovaLake #WildcatLake #PantherCove #CoyoteCove #ArcticWolf
CPUID.07h.01.EDX[22]= #SEC_TEE_ATTESTATION

AFAIK, this is news from a single source for now

#AMD #Medusa ( #Zen6 mobile) CPUID is B80F00 [1]
GitHub:
github.com/InstLatx64/I...
[1]: browser.geekbench.com/v6/cpu/17130...

Sandpile.org refreshed their CPUID page - it is a goldmine, e.g. the abandoned #AVX512 levels, MIC projects, etc.:
www.sandpile.org/x86/cpuid.htm
#AVX512QVNNI #AVX512DFMA #AVX512BITALG2 #KnightsBridge #KnightsPeak #KnightsCorner

According to this entry, #AMD #SP8 is LGA5572:
www.findchips.com/search/90446

#AMD refreshed the "Processor Programming Reference (PPR) for AMD Family 1Ah Model 02h, Revision C1 Processors" to v0.49 57238 pdf (#Zen5 CPUID B00F2x) with socket #SP6 and #TR5 infos:
docs.amd.com/v/u/en-US/57...
According to this, #EPYC8005 #Sorano is based on classic CCD, CPUID B00F2x

#AMD released the "Secure VM Service Module for SEV-SNP Guests" 58019 v1.01 pdf:
docs.amd.com/v/u/en-US/58...

#Intel Core 7 330 2P+4LPE #WildCatLake CPUID D0651 among BapCo results:
results.bapco.com/fdr/94652

Thanks, indeed, PUSH2/POP2 is not a good example of reducing code size.

To use GPR16-31, the REX2 prefix, which is 1 byte longer, is enough. MOV and LEA, for example, do not even have an EVEX version.

- All previous short instructions can still be used
- The number of MOVs is drastically reduced
- The number of loads/stores is reduced
- The number of PUSH/POPs can be halved
- Zeroing XORs are no longer needed
- CFCs instead of Jcc
2/2

It is true that the average length of each instruction increases, but it is not obvious that the code length also increases at a similar rate:
1/2

#AMD released the 10th #Zen6 pdf "AMD64 Page Modification Logging" 69208 v1.00:
docs.amd.com/v/u/en-US/69...
CPUID Fn8000_0000A_ECX[4] = Page Modification Logging

#AMD released the 9th #Zen6 pdf "AMD64 Upper Address Ignore Version 2" 69207 v1.00:
docs.amd.com/v/u/en-US/69...
Fn8000_00021_EAX[26] = UpperAddressIgnoreV2

#AMD released the 8th #Zen6 pdf "AMD64 Zen6 Instruction Based Sampling (IBS) Extensions and Features" 69205 v1.00:
docs.amd.com/v/u/en-US/69...

#AMD refreshed the "AMD64 Architecture Programmer's Manual, Volumes 1-5" 40332 to 4.09, all-in-one:
Vol1 24592-Rev. 3.24-Aug 2025
Vol2 24593-Rev. 3.44-Mar 2026
Vol3 24594-Rev. 3.37-Jul 2025
Vol4 26568-Rev. 3.26-Jan 2026
Vol5 26569-Rev. 3.16-Nov 2021
docs.amd.com/v/u/en-US/40...

I think #Darkmont is a very good update, a real Tock, for me it reminds me of the best days of #Intel.

BLENDV*s are much better with 1 or 2 uops on P02 than 4 or 8 on P0123.

My quick note about #Intel
#ArrowLake CPUID C0662 #LionCove
and
#PantherLake CPUID C06C3 #CougarCove
instruction level differences

I hope this is because all resources were directed towards developing #CoyoteCove / #PantherCove in #NovaLake and #Diamondrapids.