So proud to introduce Rayan Oliver Korbel
Posts by Max Korbel
🌉 ROHD Bridge v0.2.1 is out!
Adds support for new ROHD features, improves connectivity analysis, and tightens up robustness.
If you’re assembling large hardware designs and tired of manual wiring or brittle scripts, check out ROHD Bridge!
🔗 buff.ly/IuFHW8z
#ROHDBridge #RTL #EDA #HardwareDesign
🚀 ROHD v0.6.7 is out!
This release focuses on cleaner generated RTL, better debugability, and faster simulation—plus lots of sharp edge-case fixes.
🔗 buff.ly/IuFHW8z
#ROHD #HardwareDesign #SystemVerilog #EDA #OpenSource
After a hectic week, just finished up Day 7 (both parts), maybe can start to catch up on some of the prior ones this weekend
Got day 1 working, see my solution in ROHD on GitHub here: github.com/mkorbel1/aoc...
There's some brief write-ups in README files, might write some more later.
I'm giving "Advent of FPGA" (blog.janestreet.com/advent-of-fp... ) a shot with ROHD. I'll share my solutions and maybe some progress updates. Join my private leaderboard if you are trying it too: 3621160-1e519151
BREAKING NEWS: Sachin Katti, Intel’s chief technology and artificial intelligence officer, is leaving the chipmaker for ChatGPT creator OpenAI. www.crn.com/news/compone...
I finally got around to doing another Surfer release, so now we're on v0.4.0 🎉
My personal highlights are the new web assembly based translator system, and the improvements to our waveform control protocol, and you can read the full change log at gitlab.com/surfer-proje...
🧩 Want the details behind AI-accelerated hardware design?
Desmond Kirkpatrick’s blog shows how ROHD and LLMs enable agile, test-driven hardware evolution.
📝 buff.ly/kKimODN
Join the community 👉 buff.ly/MKcOpvD
#AI #EDA #OpenSourceHardware #Hardware #ROHD
🚀 AI isn’t just for software engineers anymore!
Intel’s Desmond Kirkpatrick shows how LLMs + the ROHD framework can assist hardware engineers in real-time design and verification.
🎥 Watch: buff.ly/VQTogJb
#AI #HardwareDesign #ROHD #AgileHardware #OpenSource #Semiconductors
I've been experimenting with using the new analyzer plugin API for code generation, and it's actually really cool!
⚡️ Instant code generation
🔬 Surgical updates in the same file
🔎 Report outdated/wrong code as lint warnings
🪄 Auto-regenerate outdated/wrong code via 'dart fix'
Announcing ROHD Bridge v0.1.2! This update comes with some big improvements based on user feedback: bug fixes, improved error messages, and more API flexibility.
See the full changelog here:
ROHD unlocks modern software patterns to generate hardware! This excellent blog post by Desmond A Kirkpatrick shows how natural it is to develop a recursive algorithm into succinct, verifiable hardware -- starting from the equivalent algorithm in software!
The ROHD Hardware Component Library (ROHD-HCL) has released v0.2.1, enhancing its features with new components like dot products, memory init, sign magnitude, more arithmetic operators, sign extension in reduction trees, typed FIFOs. Full change log: buff.ly/WHsLiGn.
Jaspr 0.21.0 is out! 🐾
It comes with:
✒️ Simpler and more Flutter-like syntax
🪄 Optimized performance and stability
🎨 More styling properties
Oh, and all breaking changes can be migrated fully automatically.
Check 🧵for details
This is so cool!
This Friday I successfully defended my PhD 🎉 If you want to watch a recording of the defense there is a recording here vimeo.com/1114208379/89dcd4f302
I tried adding a dual boot Ubuntu with Omakub (omakub.org) to my personal laptop (Dell XPS Plus 13), and it's pretty good! Surprisingly, it gets way less hot, the battery lasts longer, and things feel very snappy, I guess without the bloat.
I'm excited to share that I've joined the CHIPS Alliance governing board as the representative for Intel Corporation! I am looking forward to further contribute to open source hardware.
Announcing ROHD Bridge!! The best way to connect and assemble large hardware designs, now joining the rest of the ROHD ecosystem. ROHD Bridge is extremely fast, flexible, powerful, and modern.
See the announcement blog post for more details:
Build better hardware faster with ROHD v0.6.6! This version introduces new features for "cloning" signals and interfaces, and automates inferring and constructing matching types for structs, ports, etc. These enhancements boost type safety, consistency, and EDA development.
Want to build hardware with AI? ROHD with the new Dart MCP server is your best bet! Dart 3.9 now better supports tools like Cursor and GitHub Copilot for error fixing, dependency management, and code correction, significantly boosting HW dev. Don't miss out! Learn more about ROHD: buff.ly/2waUTww
"How do FPGAs execute blocking assignments in one clock cycle?"
Is the perfect question to frame common learning curve hurdles that folks need to get over when learning HDL.
www.reddit.com/r/FPGA/comme...
#fpga #hardware #verilog #vhdl #hdl #rtl #hls #asic #eda
This is really cool!
Announcing v0.6.4 of ROHD! It's never been a better time to accelerate the way you develop hardware.
This release has some nice bug fixes, performance enhancements, and new convenient APIs for SynthBuilder and FiniteStateMachine. Check it out!
ROHD enables some really powerful abstraction! In this video, Desmond Kirkpatrick builds and uses advanced data types for a real feature in ROHD-HCL: implementation of floating point DAZ, FTZ, and subnormal as zero!
Curious about the future of hardware design? Announcing ROHD-HCL v0.2.0!
This release has tons of new stuff, including arbitrary-width floating/fixed point arithmetics, reduction trees, clock gating, counters, finders, error correcting, standard interfaces, and much more for free! buff.ly/6eyZEOi
Pretty nice! I guess the `sliding_window` infers the `N` to keep based on what it's zipped with?
I tried to sketch something similar in ROHD to compare. Leveraged the `ShiftRegister` from the library, had to put explicit `clk` and explicit `depth`, and don't have a nice extension (yet?) for `sum`.