New Video: youtu.be/7DZ8gtORx-Y
A big round up of new and innovative products from @heber-limited.bsky.social including #misterfpga add-ons for the Multisystem, arcade #FPGA and much more.
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Adding an enable signal to 🏝️ Isle.Computer drawing engine was more of a pain than I expected, but we're now ready to share vram access with the CPU. On the plus side, this also allows you to slow the action down so you can see the drawing happen. #FPGA #verilog
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Le replay sur stream de ce matin (leds et code C sur #FPGA avec #LiteX) est maintenant disponible sur Youtube (+ la playlist à jour avec les 5 vidéos de la série):
www.youtube.com/watch?v=w4RY...
www.youtube.com/watch?v=KIH3...
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Dans 5mn on se réveille doucement en faisant clignoter des leds et avant de faire exécuter notre code par le SoC RISCV construit avec #LiteX sur notre notre #FPGA Lattice ECP5 !
www.twitch.tv/lefinnois_
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Demain dimanche 8h (CEST, pas CET😉) on continue d'explorer les #FPGA avec #LiteX. Au menu, du C, une pointe d'ASM et de l'édition de liens pour l'incontournable HelloWorld sur notre SoC #RISCV.
Et ça se passe ici : www.twitch.tv/lefinnois_
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Wir haben auf unserer GitHub Seite ein paar kleinere Schaltungen für verschiedene Vampire Karten von Apollo Computer veröffentlicht.
#commodore #amiga #amigaos #amigaworld #vampire #fpga #hardware #retro #github
github.com/AMIGAworld
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Fun in the frequency domain 🤓 Camera pointed at it's own display also showing audio FFT for cool glitchy visualizer effect. Video processing all done in PipelineC hardware. And how?
github.com/JulianKemmer...
#hardware #fpga #dsp #rtl #hdl #hls #verilog #vhdl #pipelinec
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SystemLisp - an HDL simulator written in Common Lisp
https://github.com/systemlisp
#lisp #commonlisp #hdl #rtl #verilog #design #verification #vhdl #systemverilog #vlsi #programming #fpga
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Swim (the spade build tool) now supports GateMate FPGAs.
Super cool to have a European made #fpga with official open source tools on my desk :)
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Ultimate Control Demo Shows a New Side of the Commodore 64 Ultimate
#Commodore64 #C64Ultimate #RetroComputing #GhettofingerGaming #JerryGray #FPGA #Commodore
theoasisbbs.com/ultimate-con...
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The 3dfx Voodoo 1 just got an open-source FPGA core
Hardware developer Francisco Ayala Le Brun has released SpinalVoodoo, an open-source project that recreates the classic 3dfx Voodoo 1 graphics card.
#Retro #fpga #emulation #pcgaming #3dfx
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Проект написан на относительно экзотическом SpinalHDL, который, в свою очередь, генерирует более привычный VHDL/Verilog.
Не думаю что удастся засунуть Voodoo в MiSTer, так как ядро 486 уже и так довольно толстое. Но возможно будет подспорьем для будущих FPGA-платформ.
#новости #fpga
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पिछले 30 मिनट के विषय 🧭:
1. धकर ⬆
2. नबर 🆕
3. FPGA 🆕
4. टवर 🆕
5. करत 🆕
6. सरफ 🆕
7. MWPM 🆕
8. हतर 🆕
9. टमत 🆕
10. #FPGA 🆕
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Pesquisadores de Chalmers e Gotemburgo construíram um decodificador de Rede Neural em Grafo acelerado por FPGA, alcançando latência inferior a 1μs com uma taxa de erro de 1,47×10⁻⁵ — 13% melhor que o MWPM — para códigos de superfície até distância 7.
#CorreçãoDeErrosQuânticos #FPGA #Notícias
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חוקרים מ-Chalmers וגתנבורג בנו מפענח רשת נוירונים גרפית (GNN) מואץ FPGA המשיג זמן תגובה של פחות מ-1 מיקרו-שנייה עם שיעור שגיאות של 1.47×10⁻⁵ — שיפור של 13% לעומת MWPM — עבור קודי פני שטח עד מרחק 7.
#תיקוןשגיאותקוונטי #FPGA #חדשות
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أنجز باحثو جامعتَي شالمرز وغوتنبرغ مفككًا للشبكة العصبية البيانية مُسرَّعًا بـ FPGA يحقق زمن استجابة أقل من 1 ميكروثانية بمعدل خطأ يبلغ 1.47×10⁻⁵ — أفضل بنسبة 13% من خوارزمية MWPM — لرموز السطح حتى المسافة 7.
#تصحيح_الأخطاء_الكمومية #FPGA #أخبار
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Các nhà nghiên cứu tại Chalmers và Gothenburg đã xây dựng bộ giải mã Mạng Nơ-ron Đồ thị (GNN) được tăng tốc bằng FPGA, đạt độ trễ dưới 1μs với tỷ lệ lỗi 1,47×10⁻⁵ — tốt hơn 13% so với MWPM — cho các mã bề mặt (surface codes) lên đến khoảng cách 7.
#SửaLỗiLượngTử #FPGA #TinTức
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นักวิจัยจาก Chalmers และ Gothenburg สร้างตัวถอดรหัส Graph Neural Network ที่เร่งความเร็วด้วย FPGA ซึ่งทำได้ความหน่วงต่ำกว่า 1 ไมโครวินาที พร้อมอัตราข้อผิดพลาด 1.47×10⁻⁵ ดีกว่า MWPM ถึง 13% สำหรับ surface codes ที่ระยะทางสูงสุดถึง 7
#การแก้ไขข้อผิดพลาดควอนตัม #FPGA #ข่าว
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चाल्मर्स और गोथेनबर्ग के शोधकर्ताओं ने एक FPGA-त्वरित ग्राफ न्यूरल नेटवर्क डिकोडर बनाया जो <1μs विलंबता के साथ 1.47×10⁻⁵ त्रुटि दर प्राप्त करता है — जो दूरी 7 तक के सरफेस कोड के लिए MWPM से 13% बेहतर है।
#क्वांटमत्रुटिसुधार #FPGA #समाचार
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Forscher der Chalmers- und Göteborger Universität entwickelten einen FPGA-beschleunigten Graph-Neuronales-Netz-Decoder, der eine Latenz von <1μs bei einer Fehlerrate von 1,47×10⁻⁵ erreicht — 13% besser als MWPM — für Oberflächencodes bis zur Distanz 7.
#Quantenfehlerkorrektur #FPGA #Neuigkeiten
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샬머스 & 예테보리 연구진이 거리 7까지의 표면 코드에 대해 1μs 미만의 지연 시간과 1.47×10⁻⁵ 오류율(MWPM 대비 13% 향상)을 달성하는 FPGA 가속 그래프 신경망 디코더를 개발했습니다.
#양자오류수정 #FPGA #뉴스
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チャルマース工科大学とヨーテボリ大学の研究者たちは、FPGAアクセラレーテッドグラフニューラルネットワークデコーダーを構築し、距離7までの表面符号に対して1.47×10⁻⁵の誤り率（MWPMより13%優れた結果）で1μs未満のレイテンシを達成した。
#量子誤り訂正 #FPGA #ニュース
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查爾姆斯大學與哥德堡大學的研究人員開發了一款FPGA加速圖神經網路解碼器，針對距離最大為7的表面碼，實現了低於1微秒的延遲，錯誤率為1.47×10⁻⁵，比MWPM演算法優勝13%。
#量子錯誤校正 #FPGA #新聞
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查尔姆斯大学与哥德堡大学的研究人员构建了一种FPGA加速图神经网络解码器，针对距离最大为7的表面码，实现了低于1微秒的延迟，错误率为1.47×10⁻⁵，比MWPM算法提升13%。
#量子纠错 #FPGA #新闻
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Chalmers & Gothenburg researchers built an FPGA-accelerated Graph Neural Network decoder achieving <1μs latency with a 1.47×10⁻⁵ error rate — 13% better than MWPM — for surface codes up to distance 7.
#QuantumErrorCorrection #FPGA #News
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Heh! Never seen the original. Well, neither #2 but that was all the hype for a while. I got a Voodoo 3 2000 PCI back in the day. I still have it somewhere and I wish that I didn't get rid of its box. Oh, well.
The #3dfx Voodoo Lives Again In An #FPGA
#3dfxVoodoo #RetroGaming
https:// […]
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#CloudNativeTechnologiesevolving fast and this week it’s happening at KubeCon Europe in Amsterdam. Álvaro Vázquez, Juan Poton and Carlos Giraldo are there exploring the future of cloud-native systems, from Kubernetes to edge-cloud continuum.
#CPUGPU #FPGA #NeuromorficEdgeComputing
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Work on MD+ support for the #MiSTer #FPGA #Genesis / #Megadrive continues. Everything is still coming along well.
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Hardware Acceleration Market Trends 2026: Driving Efficiency Across Industries - News Release www.prnewsreleaser.com/news/239501
#HardwareAcceleration #AI #GPU #FPGA #Semiconductor #HighPerformanceComputing #DataCenters #Innovation #Tech #Compute
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#FPGA Noodling on an AMD-Xilinx Spartan UltraScale+ SU200P design. This is a new "low(er) cost" FPGA with 64x 32KB UltraRAM blocks which hopefully will make practical manycore RISC-V FPGA overlay designs much more affordable to enthusiasts / students.
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