Verilog-Eval and RTLLM go brrr...

Finally working with local LLM inference after some bugs with vLLM

Shoutout to when I discovered that in Xilinx’s Vitis HLS 2023.1, the “help” command causes a segfault

Anytime a new version of any chip design / EDA tool is released

Automated feature testing of Verilog parsers using fuzzing I'm delighted that Quentin Corradi, a PhD student I jointly supervise with George Constantinides, will be presenting his work to improve the reliability of hardware design tools next week at the FUZZI...

Here's a short preview of a paper that Quentin Corradi, my PhD student with George Constantinides, will be presenting in the FUZZING'24 workshop at ISSTA next week... johnwickerson.wordpress.com/2024/09/09/a...

Took my research group out this week: current members and cosupervisors who could make it. One of the key privileges of working at Imperial College is the great early career researchers you get to work with.

As graduate students and avid PowerPoint users, we often encounter the most bizarre PowerPoint bugs. Recently, our PhD student, Risohv, found that emojis larger than 60pt with text shadows cause significant lag in PowerPoint. Emojis under 60pt or without shadows work fine.

We have burned many hours debugging high-level synthesis (HLS) code with subtle "ap_fixed" casting and initialization bugs. Reminder when using HLS to always explicitly cast and initialize your "ap_fixed" numbers and add a generous amount of parentheses to make order of operations explicit. #FPGA

Reminiscing back to 2023 on the first graduation of one of our earliest students, Akshay Karkal Kamath! 🎉 We are so proud of his truly budding career, currently at Apple, working on designing and implementing the next generation of chips (https://www.linkedin.com/in/akshaykamathk/

1st post on bluesky!

Reflecting on our 2023 lab outing on a hike followed by dinner to warmly welcome our newest PhD student at the time, Jiho Kim! ⛰️ 🏞️

LLNL looks to make HPC a little cloudier with Oxide's rackscale compute platform System to serve as a proof of concept for applying API-driven automation to scientific computing SC24  Oxide Computing's 2,500 pound (1.1 metric ton) rackscale blade servers are getting a new home at the Department of Energy's Lawrence Livermore…

LLNL looks to make HPC a little cloudier with Oxide's rackscale compute platform

One of our first PhD students, Rishov Sarkar (@rishovsarkar.com), successfully completed his Ph.D. proposal exam! 🎉 We had dinner to celebrate the proposal and also our celebrate our newest PhD students, Andy and Ismael!

Lots of discussion on copyright and AI right now. Check out Kate Downing’s #ICLR2024 Keynote on “Copyright Fundamentals for AI Researchers”. Lots of great insight there.

iclr.cc/virtual/2024...

Hello World!

Computing on Programmable Logic (2016):

Slides: www.microsoft.com/en-us/resear...
Video: www.youtube.com/watch?v=z1Z5...

‘Computing on Programmable Logic’ at Microsoft Research Faculty Summit 2016 Yesterday I had the privilege of speaking on Computing on Programmable Logic (slides, video) in the ‘Computing with Exotic Technologies and Platforms’ session at the Microsoft Research …

#FPGA In 2016 I had the privilege of speaking on Computing on Programmable Logic in the ‘Computing with Exotic Technologies and Platforms’ session at the Microsoft Research Faculty Summit.

Still holds up as a primer on FPGAs and their use in compute accelerators.
fpga.org/2016/07/16/c...

#FPGA Friday

OK, let's try this to show the HPC community already has momentum and can thrive here on Bluesky ...

If #HPC or #supercomputing is of interest to you, please interact with this post in some way - either repost, quote, like, reply with insights or just your fav gif, tag friends, etc.

New Vitis HLS bug unlocked! 🔑

You cannot have multiple cpp files that have the same name in the same project even if they are in different directories

They might have updated this is never versions but who knows!

Discovered by my great lab mate @rishovsarkar.com

#xilinx #fpga

Fun hardware design “bug” of the week: the SystemVerilog 2017 specs are not backwards compatible.

It introduces new keywords/reserved words, including “int” and “do” which appear as port names for many older designs, “int” referring to an init signal and “do” to mean “data out”.

#verilog

Prototype FPGA placer I wrote to learn Rust. Uses a really basic simulated annealing approach. Hope to integrate into an ongoing research project down the road. #fpga #eda #chipdesign

stefanabikaram.com/writing/fpga...

How writing HLS code feels

2GRVI Phalanx at Hot Chips 31 (2019): The First Kilocore RISC-V RV64I with High Bandwidth Memory This week at Hot Chips 31 (2019) I am presenting a status update poster on the work-in-progress GRVI Phalanx Accelerator Kit: 2GRVI Phalanx: Towards Kilocore RISC-V FPGA Accelerators with HBM2 DRAM…

#FPGA #RISCV
2GRVI Phalanx at Hot Chips 31: The First Kilocore RISC-V RV64I with HBM2 High Bandwidth Memory
fpga.org/2019/08/19/2...

Some older photos of our PI and researchers at FCCM! (The 31st IEEE International Symposium on Field-Programmable Custom Computing Machines). #academia #fpga

We want to show off our in-lab FPGA hardware:
- 8 PYNQ Boards with Xilinx Zynq-7000s
- 4 Xilinx ZCU102 Dev Boards
- 3 Raspberry Pis
All networked together so we can do multi-FPGA system experiments as well as allow remote access for our FPGA/HLS course and grad students.
#FPGA #Xilinx #comparch

Hello everone! We have migated our lab twitter account to here!

We hope to share our ongoing academic work on interdisciplinary research opportunities in the areas of ML-assisted electronic design automation (EDA), harwdare accelerators for ML, EDA-assisted hardware accelerators!