Chip Industry Week In Review AI integrity attacks; bid for Rohm; US weighs more AI chip authority; on-chip security controls; new chips at MWC; optical interconnect deals; CPO funding; 18A; diary o...

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Accellera Board Approves CDC/RDC Standard 1.0 For Immediate Release!
The Standard for IP Abstraction for Clock and Reset Domain Crossing Integration 1.0 is now available for download. Read the full press release here: bit.ly/4rabMHR #CDC/RDC #EDA #Accellera

Accellera Chair Lu Dai chats with Bill Wong of @ElectronicDesign to explore Accellera’s pivotal role in the EDA ecosystem, the real-world impact of its standards, and what’s ahead for the industry. Read the interview here bit.ly/46lKoPh #Accellera #EDA #AI #IEEE

Boosting SoC Design Productivity with IP-XACT - Semiwiki IP-XACT, defined by IEEE 1685, is a standard that pulls together IP packaging, integration, and reuse. For anyone building modern SoCs (Systems on Chip), IP-XACT isn’t just another XML schema: it is a...

Are you a chip architect navigating next-generation SoC complexity or a tool developer enabling the next gain in automation? Check out the blog by Daniel Payne in SemiWiki, “Boosting SoC Design Productivity with IP-XACT” bit.ly/4r5FdvF #Accellera #EDA #IP #SoC

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Accellera’s Portable Stimulus Working Group Chair, Matthew Ballance, offers an inside look at the enhancements in 3.1 and how they will further accelerate verification productivity across the industry. bit.ly/43aRTXM #EDA #PSS #Accellera #SoC

Moving Forward with IEEE 1800.2 UVM: Practical Insights and the Benefits of Migration Workshop presented at DVCon U.S. 2025 As the IEEE 1800.2 UVM standard continues to evolve, Accellera's release of the latest reference implementation (2020.3.1) introduces significant enhancements for verification engineers. This workshop focuses on the practical aspects of adopting the new version, providing an overview of its performance and functional improvements, as well as guidance for a smooth transition. We examine the migration process from UVM 1.2, emphasizing how the challenges faced in earlier transitions have been addressed. Particular attention is given to backward compatibility and resources now available, such as the public GitHub repository, which supports faster delivery of bug fixes and migration aids. Viewers will also gain an understanding of the performance benefits introduced and how these enhancements can accelerate verification workflows compared to legacy versions. The workshop also provides an overview of functional improvements, including enhancements that reduce the need to maintain modified versions of the UVM library. Finally, we discuss potential future enhancements, including plans for reworking the Register Abstraction Layer (RAL). Presented by: Justin Refice, NVIDIA https://dvcon.org https://dvcon-proceedings.org https://accellera.org https://ieee.org

New Video Available! “Moving Forward with IEEE 1800.2 UVM: Practical Insights and the Benefits of Migration” presented at DVCon U.S. 2025

View on Accellera’s YouTube Channel bit.ly/4eRpavE #UVM #Accellera #IEEE

Lu Dai on Accellera’s AI-Driven Standards and Upcoming DAC Events In this exclusive interview, Sanjay Gangal of Sanjay Tech Cafe speaks with Lu Dai, Chair of Accellera, about the organization’s pivotal role in shaping the front-end EDA standards landscape. Lu provides a deep dive into Accellera’s mission, widely adopted standards like SystemC, UVM, and UPF, and the organization’s expanding focus on AI’s impact in design and verification. Lu also highlights Accellera’s presence at DAC 2025, including the highly anticipated AI-focused luncheon panel featuring leaders from Cadence, AMD, Siemens, Synopsys, Microsoft, and NVIDIA. He previews the special engineering session on CDC and RDC standards, discusses the open and collaborative development approach, and invites viewers to engage, contribute feedback, and access resources such as IEEE 1801 and training videos via accellera.org. If you're involved in EDA, chip design, or system verification, this is a must-watch conversation on how standards are evolving to keep pace with AI and industry innovation. 👉 Don’t forget to like, comment, and subscribe for more in-depth industry interviews!

Exciting insights from Lu Dai, Chair of Accellera, in a conversation with Sanjay Gangal as they discuss Accellera’s upcoming luncheon focused on AI in Design and Verification at #62DAC and more! See the video @Sanjaytechcafe on YouTube bit.ly/4jMhDiE #Accellera #EDA #AI

Introduction of IEEE 1801-2024 (UPF 4.0) -- For Specification and Verification of Low-Power Intent Workshop presented at DVCon U.S. 2025 Full title: Introduction of IEEE 1801-2024 (UPF 4.0) -- Improvements for the Specification and Verification of Low-Power Intent As advanced low-power architectures have become more pervasive in the industry, the complexity of these architectures has driven new methodologies for the verification, implementation, and reuse of power intent specifications. Modern low-power designs place requirements that span from enabling more flexible IP design reuse to providing well defined interfaces between analog and digital components in simulation. The IEEE 1801-2024 (UPF 4.0) standard provides several key enhancements that are required to keep pace with these innovations in low-power design. The workshop provides an overview of the enhancements to the standard from both a conceptual and a command level. New concepts such as virtual supply nets, refinable macros, and UPF libraries are introduced, as well as rearchitected features with respect to interfacing between analog and digital simulation and advanced state retention modeling. While the new IEEE 1801-2024 standard provides numerous detailed clarifications and enhancements to the previous version, this workshop focuses on the key changes that will impact most designers and changes that enable new functionality. In the six years since IEEE 1801-2018 was introduced, there have been a number of trends in design that required additional features in the standard to support. Key among these is an increasing need for co-verification of analog and mixed-signal content. Another trend is that IP providers are providing pre-verified low-power IP to their customers, but struggle to provide a flexible IP for implementation in multiple design contexts while preserving the verification sign-off on the blocks. To address these trends, IEEE 1801-2024 provides new features such as Value Conversion Methods (VCM) and HDL tunneling that help bridge the gap between the analog and digital designs, and the concept of a refinable macro to address the IP reuse requirements. Real-world usage of the previous standard (IEEE 1801-2018) has prompted clarifications and enhancements that will have a significant impact on users of the standard. For example, the modeling of state retention has been entirely reworked to provide better modeling of the retention power intent and to more accurately define requirements on the retention control signals in each phase of state retention. The new standard also codifies some common design practices to make a clear, more consistent implementation across vendors. The new concept of virtual supplies is one such case. It removes the ambiguity that exists today when supplies are used to provide port constraints or to simplify power state definitions, but do not imply a physical supply net in implementation. This workshop introduces these new concepts and their associated commands and provides an overview of the major semantic and syntax changes introduced by IEEE 1801-2024. This understanding will help users transition to the new standard and improve the quality of advanced low-power architectures and design environments. Authors: -- John Decker, IEEE P1801 Workgroup Chair -- Daniel Cross, Cadence -- Amit Srivastava, IEEE P1801 Workgroup Vice-Chair -- Lakshmanan Balasubramanian, IEEE P1801 Workgroup Secretary -- Marcelo Glusman, Cadence -- Medaramitta Jeevan, Siemens -- Gabriel Chidolue, Siemens -- Rick Koster, Siemens -- Raguvaran Easwaran, Intel -- Paul Bailey, Nordic Semiconductor -- Progyna Khondkar, Cadence https://dvcon.org https://dvcon-proceedings.org https://accellera.org https://ieee.org

NEW VIDEO! Explore the latest enhancements to IEEE 1801™-2024 (UPF 4.0) in the workshop from DVCon U.S. 2025 now available to view on demand! Watch now on Accellera's YouTube channel: bit.ly/4561dOG

#IEEE #Accellera #UPF #LowPowerDesign #DVCon_US #IP

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Check out what Accellera is up to @ the 62nd DAC, the launch of the SystemC Summer of Code Program, free access to IEEE 1801-2024 via the GET Program, and so much more in the May Accellera newsletter. Check it out bit.ly/3SkgSlL #Accellera #SystemC #DVCon #IEEE #62DAC

Join Accellera at #62DAC for an exciting discussion among AI design & verification leaders. The luncheon on June 24 at noon is free to attend, but registration is required. For more info and to register: bit.ly/3URnybF #AI #EDA #Standards #Accellera #IP #SemiWiki.com

Accellera Welcome to Accellera Systems Initiative's official YouTube channel. Accellera is an independent and collaborative organization with the mission to create and advance system-level design, modeling, a...

Explore hundreds of videos covering the latest in design and verification standards, technical presentations, and working group insights — all available anytime, on demand. Subscribe to Accellera’s YouTube channel and dive into what interests you: bit.ly/44fLBHT #Accellera #EDA #Standards #DVCon

An Inside Look At UPF 4.0 Why the Unified Power Format is necessary for verifying leading-edge designs.

Interested in low power? Check out Barry Pangrle’s article “An Inside Look at UPF 4.0” in Semiconductor Engineering bit.ly/3RZl9e1 #IEEE #Accellera #UPF #EDA

Drafts Under Public Review

CDC Draft Standard 0.5 Available for Public Review through May 15! The standard is aimed at simplifying Clock and Reset Domain Crossing in SoCs.
Download the CDC Draft Standard 0.5: bit.ly/3tdwMpe
Provide feedback Community Forum: bit.ly/42vYdb4
#CDC #EDA #IP #IPXACT #Accellera #Standards

Want the latest news from Accellera delivered straight to your inbox? Subscribe to our quarterly newsletter. Just visit the Accellera home page www.accellera.org and add your email under the Featured Events box and we’ll be sure to keep you in the loop! #Accellera #EDA

Accellera Announces IEEE Standard 1801™-2024 is Available Through IEEE GET Program

The IEEE Std. 1801™-2024 Unified Power Format (UPF) 4.0 is now available for download fee-free through the IEEE GET Program, courtesy of Accellera! For more info, including a link to download, read the press release: bit.ly/4iVcGEc #Accellera #UPF #IEEE #EDA #ASIC

CDC Working Group 2025 Update Members of the Accellera CDC (Clock Domain Crossing) Working Group share the history, accomplishments, and current status of the working group. For an extended version, see: https://www.youtube.com/watch?v=k52ED1FxyrU

Want to learn more about Accellera’s Clock Domain Crossing Working Group? Members share the history, benefits of the standard, accomplishments, and status of the WG. Check out the video on Accellera’s YouTube channel bit.ly/4hDcKr1 #Accellera #EDA #SoC

Register for the upcoming SystemC Evolution Fika to be held March 27 16:00-18:00 CET. The online workshop focused on the evolution of SystemC standards is free to attend. For the agenda and registration information visit bit.ly/3FjKBYB. #SystemC #Accellera

Accellera Chair Lu Dai shows his support for DVCon U.S. 2025! For more on DVCon U.S. 2025 visit dvcon.org For more on Accellera events around the globe visit accellera.org/news/events #DVCon_US #Accellera #EDA #Verification #standards

Federated Simulation

Accellera's Federated Simulation Standard (FSS) White Paper now available! Different industries are tackling modeling and simulation challenges in silos leading to fragmented and incompatible standards. FSS aims to bridge these gaps. Learn more in the white paper bit.ly/41swg4H #FSS #Accellera #EDA

Accellera Announces SystemC Summer of Code Program. Students with experience and a passion for C++ programming are invited to contribute to the evolution of the SystemC ecosystem. Read the press release bit.ly/439YJ0Hvisi; the SystemC Community Portal systemc.org for more info #SystemC #Accellera

Karsten Einwich Honored with Accellera’s 2025 Technical Excellence Award!
He has played a pivotal role in advancing the SystemC AMS standard, contributing to the definition of IEEE Std. 1666.1. Congratulations Karsten!
More info: bit.ly/4gSRld0
#SystemC #AMS #TechnicalExcellence #Accellera #IEEE

Introduction of IEEE 1801-2024 (UPF4.0) improvements for the specification and verification of low-power intent | DVCON 2025 The Design & Verification Conference & Exhibition (DVCON 2025) is the premier conference on the application of languages, tools, methodologies and standards for the design and verification of electron...

Learn more about UPF 4.0 at DVCon U.S. 2025 during the workshop “Introduction of IEEE 1801-2024 (UPF 4.0)” on Feb 24 @ 9am. Explore the key advancements in the standard. bit.ly/41hfOEy More Accellera events at DVCon bit.ly/4aTh1F3 #IEEE #UPF #DVCon_US #Accellera

Scholarship

Accellera’s Stanley J. Krolikoski Scholarship for Electrical Engineering and Computer Science Students is now accepting applications! For more info & application: bit.ly/49IN1Kz. Please share the link to those that might be interested. #Accellera #Scholarship #ComputerScience #ElectricalEngineering

Chip Industry Week In Review Industry growth reports; new GF CEO; UVM for mixed signal; power dem...

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#Business #Business #News #News #3M #Accellera #Accuron #Technologies #Advantest #AI #Alea

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