How to handle coherent DMA?
A coherent DMA operation that reads memory should get the most recent version of data, even if the data resides in a cache in state M or O. Similarly, a coherent DMA operation that writes memory must invalidate stale copies in all caches. Though it is straightforward to handle coherent DMA by adding a coherent cache to the DMA controller, it it not desirable for a couple of reasons:
In this post, let's discuss what is the best way to handle coherent DMA.
#DMA #CacheCoherent
