We use Claude Code extensively in debugging DV tests, and it works really well. In our project-level CLAUDE.md, we clearly document how RTL, TB and C-model are structured to provide Claude Code some guidance, such that it won’t search the entire code base every single time.

#ClaudeCode #Debug #DV

Claude Code's context window is not unlimited, and the performance degrades quickly as it fills up. In our "CLAUDE.md", the 1st rule is to ask it always respond with our name. If Claude Code forgets to call "Chipress", we know it's time to start a new conversation.

#ClaudeCode #AI #RTLDesign

Best Practices for Claude Code - Claude Code Docs Tips and patterns for getting the most out of Claude Code, from configuring your environment to scaling across parallel sessions.

We've been using Claude Code for our real work in the past few weeks, and found it's quite a powerful tool for hardware engineers. This post from Anthropic explains best practice of using Claude Code. We recommend everyone to check it out.

code.claude.com/docs/en/best...

#ClaudeCode #AI #RTLDesign

How to write efficient DV constraints? Split Bigger Problem into Smaller Ones Instead of mixing everything together, splitting bigger problems into smaller steps offers better performance. One may consider using “Solve-Before” for user defined solving order. In addition, it is also recommended to sequence constraint solving in “pre_randomize()” and “post_randomize()” whenever possible. Use “Solve-Before” with Caution Although user-defined “

In this post, we will share a few tips and tricks of writing efficient DV constraints for better simulation performance.

#Constraints #Simulation #DV

What can cause a simulation hang? Simulation hang is a condition where simulator functionalities cannot advance. We can only observe that nothing meaningful has happened for a long time. Simulation hang can be caused by RTL bugs, testbench (TB) issues, or C-model errors. RTL Bugs A combinational loop in RTL can prevent time from advancing. When there exists a combinational loop in RTL, the “always_comb…

Simulation hang can be caused by RTL bugs, TB issues, or C-model errors. Let's explore the hang root causes in detail.

#simulation #hang

How to spot toxic managers before accepting an offer? Most people only realize the manager is toxic after on-boarding, when the switching costs are too high. They did not realize, toxic managers often reveal themselves during the interview process, if they know what to ask and what to look for. Patterns of Toxic Managers The most common type of toxic managers looks like this: During project planning, they do not provide clear requirements…

Most people only realize the manager is toxic after on-boarding, when the switching costs are too high. They did not realize, toxic managers often reveal themselves during the interview process, if they know what to ask and what to look for.

#Interview #Manager #Toxic

What are LEC abort points? How to debug aborts? It is not uncommon to see abort points during LEC. They are the key points that have not been proven either equivalent or non-equivalent based on the current tool settings, such as compare effort or compare algorithms. There are several possible causes of abort points: Don’t Care conditions, such as out-of-range index and X-assignments. They can increase complexity for comparison.

It's not uncommon to see abort points during LEC. This post shows a few possible causes of aborts and how to debug aborts.

#LEC #LEQ #Aborts

How to improve re-build time during test case development? During test case development, the trial and error process often causes re-compilation and re-elaboration of the entire database, including testbench (TB), DUT, C-model, and sometimes even UPF if it is for power-aware verification. When the database is large, rebuilding everything is time consuming. There are several ways to optimize re-build time during test case development. Split Compilation on TB and DUT…

During test case development, rebuilding everything is time consuming. We discussed 3 ways to optimize rebuild time.

#DV #Testcase #BuildTime

Semiconductor ATE Testing: Why Every Chip Needs a Test I. The Imperative of Testing: Quality, Cost, and Reliability Semiconductor testing is a non-negotiable step in modern manufacturing, driven by quality, reliability, and cost control. The key tool is the Automatic Test Equipment (ATE), a sophisticated, computer-controlled machine that runs software to apply electrical signals and verify a chip's performance. The Necessity of Testing Testing is a delicate economic trade-off between maximizing production…

Our guest author, Deepak M E, shares his 2nd post on our platform. It discusses the necessity, the evolution and the future of chip testing. Check out his insights in the post!

#PDE #DFT #ATE

cache-coherent – Chipress Posts about cache-coherent written by chipressian

We have compiled a series of posts on cache coherency during the past few months. Understanding cache coherency protocols is crucial in understanding how multi-threaded programs execute in a shared memory system. Check us out!

chipress.online/tag/cache-co...

#Cache #CacheCoherency #MemoryModels

The Bridge Builders: A Guide to Landing the Product Development Engineer Role in Semiconductors The modern world runs on silicon. Every advanced device, from your phone's processor to the chip in a self-driving car, relies on flawless, high-volume manufacturing. This is where the Product Development Engineer (PDE) steps in. They're the critical bridge. They are the ultimate product owner. They guide an integrated circuit (IC) from its first silicon sample through to profitable, mature mass production.

Our guest author, Deepak M E, is an experienced product development engineer from Google. His first post in Chipress Academy, shares his insights to land a product development engineer role in the semiconductor industry. This would be a great guide for whoever desires to enter the PDE world.

How to resolve SVA false failure with gated clocks? In FPV, if an SVA uses a gated clock, it could have false failures. Take the following SVA for example: // clk_gated does not toggle when block_busy == 0 assert property (@(posedge clk_gated) block…

How to resolve SVA false failure with gated clocks? chipress.online/2025/10/05/h...

Sometimes we may see false failures of SVAs using gated clock. We will discuss how to resolve these false failures in this post.

#SVA #ClockGating #FV

What is a valid-ready slice staller? How does a staller work? In simulations, testbench may intentionally inject bubbles to a valid-ready interface, to check that the valid-ready interface can still functionally work. Such technique is called valid-ready slice staller, and it improves the coverage of valid-ready interface backpressure scenarios. One possible staller implementation is shown below: Valid-ready staller In the regular case, “stall_en” is low, and the staller is functionally transparent in the datapath; When enabling the staller, testbench will drive “stall_en” high, and the valid-ready interface is stalled. Testbench can randomly drive “stall_en” on a per cycle basis during simulation.

Valid-ready staller is a useful simulation technique to inject bubbles and improve design robustness. Let's discuss how it works.

#ValidReady #staller #simulation #DV

How to optimize coherence conflict / false sharing? Coherence conflict happens when two cores compete for the read & write access for the cache line. False sharing, in particular, is a special type of coherence conflict, where two cores read and write different data that happen to reside in the same cache line. The coherence traffic incurred by coherence conflict / false sharing hurts performance when a core is waiting for coherence permissions for data access, and increases the load on the interconnection network / fabric.

Coherence conflict and false sharing are some of the common cases we should optimize when implementing cache coherence protocols. Let's see how to optimize it.

#Cache #CacheCoherence #CoherenceConflict #FalseSharing

How to handle coherent DMA? A coherent DMA operation that reads memory should get the most recent version of data, even if the data resides in a cache in state M or O. Similarly, a coherent DMA operation that writes memory must invalidate stale copies in all caches. Though it is straightforward to handle coherent DMA by adding a coherent cache to the DMA controller, it it not desirable for a couple of reasons:

In this post, let's discuss what is the best way to handle coherent DMA.

#DMA #CacheCoherent

What are the advantages and disadvantages of using write-through cache in cache coherence protocol? We assumed using write-back caches in cache coherence protocols. It is possible to use write-through caches as well. Advantages of using write-through caches: A significantly simpler two-state coherence protocol (Valid and Invalid). Stores write through the Last Level Cache (LLC) / memory, and invalidate all valid copies in other caches An L1 cache eviction requires no action besides changing the L1 state to Invalid, since LLC / memory always hold up-to-date data…

We assumed using write-back caches in cache coherence protocols. It is possible to use write-through caches as well. Let's discuss the pros and cons of using write-through cache in cache coherence protocols.

#Cache #CacheCoherence

We (chipress.online/blog-posts/) have published several posts on cache coherence implementation with non-atomic operation handling. At school, such topics will be barely covered; but they are critical in real world implementation.

Check it out if you are interested!

#CacheCoherency #Cache #Atomic

Handling non-atomic requests in directory based MSI protocol (II) In the previous post, we discussed about handling non-atomic requests in directory based MSI protocol by stalls. In cache controller transient states such as “IS-D”, “IM-A” and “SM-A”, we could allow forwarded request messages to make progress without stalling, at the expense of adding more transient states. For example, when a cache controller has a line in State “IS-D” and receives an Inv message, it processes the request and changes the line’ state to “IS-D-I”, indicating the cache controller should change the line state to I after the “GetS” transaction completes.

In non-atomic requests handling in directory based MSI protocol, one can allow forwarded requests to make progress without stalling. Let's discuss how to achieve that in this post.

#CacheCoherency #Cache #MSI #Snoop

Claude Code Best Practices A blog post covering tips and tricks that have proven effective for using Claude Code across various codebases, languages, and environments.

Claude CLI is a powerful AI tool for understanding codebase, code editing and workflow automation. This post from Anthropic shows a few best practices of using Claude CLI. It's definitely a recommended reading.

www.anthropic.com/engineering/...

We found an interesting reading online: "How to Think About GPUs".

It talks about Nvdia GPU architecture, and introduces rooflines for LLM scaling on GPUs. Check it out if you are interested.

jax-ml.github.io/scaling-book...

Handling non-atomic requests in directory based MSI protocol (I) Just like snooping based protocols, directory based cache coherence protocol has to handle non-atomic requests in real world implementations. We start from the a directory based MSI base model, and discuss one solution on non-atomic requests handling. Base Model In directory based MSI protocol, there are 3 message types: Request messages, including GetS, GetM, PutM and PutS Forwarded request messages, including Fwd-GetS, Fwd-GetM, Inv (Invalidation), and Put-Ack…

In real world implementation of directory based MSI protocol, properly handling of non-atomic requests is required. Let's see how to achieve that (by stalls) in this post.

#CacheCoherency #Cache #MSI #Snoop

Handling non-atomic operations in snooping based MSI protocol (II) In the previous post, we discussed non-zero delay from coherence requests to responses. However, coherence requests may also be non-atomic: a coherence request may not be instantly ordered when it is issued by a cache controller. For example, if there is a request queue between a cache controller and the system bus, coherence request atomicity is no longer guaranteed, and this is a fairly common implementation.

Implementing snooping based MSI protocol should consider non-atomic coherence requests as well. Let's see how address non-atomic coherence requests.

#CacheCoherency #Cache #MSI #Snoop

How to implement hardware for array sorting in ascending order (III) – Using Linear Algebra? In a previous post, we discussed one possible array sort solution without comparators. There are more comparison-free array sorting implementations available. In paper “An Efficient O(N) Comparison…

How to implement hardware for array sorting in ascending order (III) - Using Linear Algebra?

Using linear algebra is another interesting comparator-free sorting solution. Check it out!

#ASIC #RTL #Sorting #Sort

chipress.online/2024/05/01/h...

How to implement hardware for array sorting in ascending order (II) – Without Comparator? In a previous post, we discussed hardware implementation for array sorting using comparators. However, it is also possible to sort arrays without comparators. Surajeet Ghosh, Shaon Dasgupta and San…

How to implement hardware for array sorting in ascending order (II) - Without Comparators?

We discussed hardware implementation for array sorting using comparators. However, it is also possible to sort arrays without comparators.

#ASIC #RTL #Sorting #Sort

chipress.online/2024/04/30/h...

How to implement hardware for array sorting in ascending order (I) – With Comparator? Implementing hardware based array sorting is frequently asked when interviewing with high frequency trading companies. There are quite a few software based sorting algorithms that hardware implemen…

How to implement hardware for array sorting in ascending order (I)

Implementing array sorting in hardware is a hot interview topic for high frequency trading companies. Software based sorting can be leveraged by hardware.

#ASIC #RTL #Sorting #Sort

chipress.online/2024/04/29/h...

Handling non-atomic operations in snooping based MSI protocol (I) In cache coherence protocol implementation, designers must properly handle non-atomic operations, since coherence transactions cannot complete instantly. We start from the well-known snooping based…

Handling non-atomic operations in snooping based MSI protocol (I) chipress.online/2025/07/25/h...

In real-world cache coherence implementation, designers must properly handle non-atomic operations. This is often overlooked, and we'll expand this topic in detail.

#CacheCoherency #Cache #MSI #Snoop

A Must Read List of Papers for ASIC Design Interviews Yet Another Latch and Gotchas Paper by Don Mills This paper discusses several SystemVerilog coding topics that can lead to inadvertent design bugs, including casex / casez expressions and unique / …

A Must Read List of Papers for ASIC Design Interviews chipress.online/2024/04/10/a...

In this post, we share a few must-read list of papers for ASIC design interviews. You might find these papers helpful in your interview preparations.

#ASIC #SOC #RTL #Interview

Understanding Power Analysis & Estimation: 2 Recommended Readings As SoCs are getting more complex, power becomes just as important as functionality correctness or performance. This article, “Unified Methodology for Effective Correlation of SoC Power Estimation and Signoff" by Infineon Technologies, addresses the growing challenges in accurately estimating and correlating power in complex SoCs. This article is a good start to understand how the ASIC industry handles power concerns intelligently and early.

In this post, we recommend two readings to help people better understanding how power analysis flow works and how power estimation is done. Check this out!

#Power #PowerAnalysis #PowerEstimation

Python 2 has gradually been deprecated, and developers are encouraged to migrate to Python 3. Luckily, for Python 2 legacy program, there is a way to automatically convert to Python 3. Check out this link: python3porting.com/2to3.html

What we learnt from Gemini Prompting Guide 101 Google released its “Gemini Prompting Guide 101” a while ago. Though the majority of the examples in this guide use Google Workspace for illustration purposes, it still provides a general ideal of writing effective prompts for all LLMs. The guide Four first illustrates the 4 main areas for effective prompts: Persona, i.e., assign a role to LLM to encourage creativity…

Google released its “Gemini Prompting Guide 101” a while ago. Though the majority of the examples in this guide use Google Workspace for illustration purposes, it still provides a general ideal of writing effective prompts for all LLMs. We encourage every to check it out.

#LLM #AI