How to optimize coherence conflict / false sharing?
Coherence conflict happens when two cores compete for the read & write access for the cache line. False sharing, in particular, is a special type of coherence conflict, where two cores read and write different data that happen to reside in the same cache line. The coherence traffic incurred by coherence conflict / false sharing hurts performance when a core is waiting for coherence permissions for data access, and increases the load on the interconnection network / fabric.
Coherence conflict and false sharing are some of the common cases we should optimize when implementing cache coherence protocols. Let's see how to optimize it.
#Cache #CacheCoherence #CoherenceConflict #FalseSharing
