#CacheCoherence

CPU Caches: Why tiny memory matters? System design

Multi-core CPUs: it’s a game of telephone, but everyone keeps receipts. Cache coherence (MESI, MOESI, MESIF) keeps every core in sync as they race to update data. If only teamwork scaled this well. Ever debugged a cache bug? ...
#CPUs #CacheCoherence #Programming

How to optimize coherence conflict / false sharing? Coherence conflict happens when two cores compete for the read & write access for the cache line. False sharing, in particular, is a special type of coherence conflict, where two cores read and write different data that happen to reside in the same cache line. The coherence traffic incurred by coherence conflict / false sharing hurts performance when a core is waiting for coherence permissions for data access, and increases the load on the interconnection network / fabric.

Coherence conflict and false sharing are some of the common cases we should optimize when implementing cache coherence protocols. Let's see how to optimize it.

#Cache #CacheCoherence #CoherenceConflict #FalseSharing

What are the advantages and disadvantages of using write-through cache in cache coherence protocol? We assumed using write-back caches in cache coherence protocols. It is possible to use write-through caches as well. Advantages of using write-through caches: A significantly simpler two-state coherence protocol (Valid and Invalid). Stores write through the Last Level Cache (LLC) / memory, and invalidate all valid copies in other caches An L1 cache eviction requires no action besides changing the L1 state to Invalid, since LLC / memory always hold up-to-date data…

We assumed using write-back caches in cache coherence protocols. It is possible to use write-through caches as well. Let's discuss the pros and cons of using write-through cache in cache coherence protocols.

#Cache #CacheCoherence