GitHub - MidstallSoftware/aegis: Open source FPGA silicon Open source FPGA silicon. Contribute to MidstallSoftware/aegis development by creating an account on GitHub.

🦾 Aegis: Open source FPGA silicon

github.com/MidstallSoft...

#fpga #opensource

Et... la vidéo du stream de ce matin est disponible sur Youtube. Petit voyage dans les coulisses du linker et victoire final pour utiliser les 8 Mio de SDRAM avec notre code en C \o/ #FPGA #LITEX
www.youtube.com/watch?v=Fi0x...

Victoire \o/ La carte Colorlight a subi sa transplantation de SDRAM avec succès, 8Mio (M12L64322A) -> 32 Mio (IS42S32800) et le mem_test semble positif. Quelques étranges problèmes d'alimentation (ou de bruit) subsistent, WIP donc... #FPGA #LITEX

Lefinnois_ - Twitch Lefinnois_ streams live on Twitch! Check out their videos, sign up to chat, and join their community.

Dans 5 minutes on fouille dans la mémoire de notre SoC #RISCV sur #FPGA ECP5 avec #LITEX...
www.twitch.tv/Lefinnois_

Lefinnois_ - Twitch Lefinnois_ streams live on Twitch! Check out their videos, sign up to chat, and join their community.

Demain on remet le couvert avec notre #FPGA Lattice ECP5 avec #LiteX et on va creuser dans la mémoire, l'éditeur de liens et le crt0.S pour utiliser les 8 Mio de SDRAM. Et ça se passe sur Twitch à 8 heures pétantes: www.twitch.tv/lefinnois_

今日はブログ記事書く日かな。
#FPGA

It’s here! #superstationone #fpga

Earthrise 2D drawing test image on widescreen monitor driven by an FPGA dev board over HDMI. A mixture of lines, triangles, and circles in greens and oranges.

The drawing engine refactor was getting chunky, so I merged it. If you want to have a play, there are a few (not enough) details on the 🏝️ Isle.Computer blog: projectf.io/isle/2d-draw...

This refactor will allow me to share vram between CPU and drawing engine for the first Isle release. #FPGA

wolfTPM now enables firmware TPM (fTPM) support.
- TPM 2.0 command support
- TrustZone, FPGA, and isolated core deployments
- Measured boot & remote attestation
- FIPS 140-3 crypto options
Built for embedded security at scale 🔐

Learn more: www.wolfssl.com/anno...
#TPM #fTPM #FIPS #FPGA

Couldn't resist trying some colors too! Also here's a flatter top design #fpga

New Video: youtu.be/7DZ8gtORx-Y

A big round up of new and innovative products from @heber-limited.bsky.social including #misterfpga add-ons for the Multisystem, arcade #FPGA and much more.

Adding an enable signal to 🏝️ Isle.Computer drawing engine was more of a pain than I expected, but we're now ready to share vram access with the CPU. On the plus side, this also allows you to slow the action down so you can see the drawing happen. #FPGA #verilog

Le replay sur stream de ce matin (leds et code C sur #FPGA avec #LiteX) est maintenant disponible sur Youtube (+ la playlist à jour avec les 5 vidéos de la série):
www.youtube.com/watch?v=w4RY...
www.youtube.com/watch?v=KIH3...

Lefinnois_ - Twitch Lefinnois_ streams live on Twitch! Check out their videos, sign up to chat, and join their community.

Dans 5mn on se réveille doucement en faisant clignoter des leds et avant de faire exécuter notre code par le SoC RISCV construit avec #LiteX sur notre notre #FPGA Lattice ECP5 !
www.twitch.tv/lefinnois_

Twitch Twitch is the world

Demain dimanche 8h (CEST, pas CET😉) on continue d'explorer les #FPGA avec #LiteX. Au menu, du C, une pointe d'ASM et de l'édition de liens pour l'incontournable HelloWorld sur notre SoC #RISCV.
Et ça se passe ici : www.twitch.tv/lefinnois_

Wir haben auf unserer GitHub Seite ein paar kleinere Schaltungen für verschiedene Vampire Karten von Apollo Computer veröffentlicht.

#commodore #amiga #amigaos #amigaworld #vampire #fpga #hardware #retro #github

github.com/AMIGAworld

Fun in the frequency domain 🤓 Camera pointed at it's own display also showing audio FFT for cool glitchy visualizer effect. Video processing all done in PipelineC hardware. And how?

github.com/JulianKemmer...

#hardware #fpga #dsp #rtl #hdl #hls #verilog #vhdl #pipelinec

systemlisp - Overview An experimental HDL simulator written in Common Lisp focused on interactive and extensible hardware design and verification. - systemlisp

SystemLisp - an HDL simulator written in Common Lisp

https://github.com/systemlisp

#lisp #commonlisp #hdl #rtl #verilog #design #verification #vhdl #systemverilog #vlsi #programming #fpga

Swim (the spade build tool) now supports GateMate FPGAs.

Super cool to have a European made #fpga with official open source tools on my desk :)

Ultimate Control Demo - The Oasis BBS Ultimate Control Demo shows Jerry Gray using C64 Ultimate Control to manage the Commodore 64 Ultimate from an iPad.

Ultimate Control Demo Shows a New Side of the Commodore 64 Ultimate
#Commodore64 #C64Ultimate #RetroComputing #GhettofingerGaming #JerryGray #FPGA #Commodore

theoasisbbs.com/ultimate-con...

The 3dfx Voodoo 1 just got an open-source FPGA core Hardware developer Francisco Ayala Le Brun has released SpinalVoodoo, an open-source project that recreates the classic 3dfx Voodoo 1 graphics card.

The 3dfx Voodoo 1 just got an open-source FPGA core

Hardware developer Francisco Ayala Le Brun has released SpinalVoodoo, an open-source project that recreates the classic 3dfx Voodoo 1 graphics card.

#Retro #fpga #emulation #pcgaming #3dfx

Проект написан на относительно экзотическом SpinalHDL, который, в свою очередь, генерирует более привычный VHDL/Verilog.

Не думаю что удастся засунуть Voodoo в MiSTer, так как ядро 486 уже и так довольно толстое. Но возможно будет подспорьем для будущих FPGA-платформ.

#новости #fpga

पिछले 30 मिनट के विषय 🧭:

1. धकर ⬆
2. नबर 🆕
3. FPGA 🆕
4. टवर 🆕
5. करत 🆕
6. सरफ 🆕
7. MWPM 🆕
8. हतर 🆕
9. टमत 🆕
10. #FPGA 🆕

Decodificador GNN Acelerado por FPGA Quebra o Trade-off entre Velocidade e Precisão na Correção de Erros Quânticos

Pesquisadores de Chalmers e Gotemburgo construíram um decodificador de Rede Neural em Grafo acelerado por FPGA, alcançando latência inferior a 1μs com uma taxa de erro de 1,47×10⁻⁵ — 13% melhor que o MWPM — para códigos de superfície até distância 7.

#CorreçãoDeErrosQuânticos #FPGA #Notícias

מפענח GNN מואץ FPGA שובר את הפשרה בין מהירות לדיוק בתיקון שגיאות קוונטי

חוקרים מ-Chalmers וגתנבורג בנו מפענח רשת נוירונים גרפית (GNN) מואץ FPGA המשיג זמן תגובה של פחות מ-1 מיקרו-שנייה עם שיעור שגיאות של 1.47×10⁻⁵ — שיפור של 13% לעומת MWPM — עבור קודי פני שטח עד מרחק 7.

#תיקוןשגיאותקוונטי #FPGA #חדשות

مفكك GNN المُسرَّع بـ FPGA يكسر المقايضة بين السرعة والدقة في تصحيح الأخطاء الكمومية

أنجز باحثو جامعتَي شالمرز وغوتنبرغ مفككًا للشبكة العصبية البيانية مُسرَّعًا بـ FPGA يحقق زمن استجابة أقل من 1 ميكروثانية بمعدل خطأ يبلغ 1.47×10⁻⁵ — أفضل بنسبة 13% من خوارزمية MWPM — لرموز السطح حتى المسافة 7.

#تصحيح_الأخطاء_الكمومية #FPGA #أخبار

Bộ Giải Mã GNN Tăng Tốc FPGA Phá Vỡ Đánh Đổi Giữa Tốc Độ và Độ Chính Xác trong Sửa Lỗi Lượng Tử

Các nhà nghiên cứu tại Chalmers và Gothenburg đã xây dựng bộ giải mã Mạng Nơ-ron Đồ thị (GNN) được tăng tốc bằng FPGA, đạt độ trễ dưới 1μs với tỷ lệ lỗi 1,47×10⁻⁵ — tốt hơn 13% so với MWPM — cho các mã bề mặt (surface codes) lên đến khoảng cách 7.

#SửaLỗiLượngTử #FPGA #TinTức

ตัวถอดรหัส GNN ที่เร่งความเร็วด้วย FPGA ทำลายข้อจำกัดระหว่างความเร็วและความแม่นยำในการแก้ไขข้อผิดพลาดควอนตัม

นักวิจัยจาก Chalmers และ Gothenburg สร้างตัวถอดรหัส Graph Neural Network ที่เร่งความเร็วด้วย FPGA ซึ่งทำได้ความหน่วงต่ำกว่า 1 ไมโครวินาที พร้อมอัตราข้อผิดพลาด 1.47×10⁻⁵ ดีกว่า MWPM ถึง 13% สำหรับ surface codes ที่ระยะทางสูงสุดถึง 7

#การแก้ไขข้อผิดพลาดควอนตัม #FPGA #ข่าว

FPGA-त्वरित GNN डिकोडर ने क्वांटम त्रुटि सुधार में गति-सटीकता के समझौते को तोड़ा

चाल्मर्स और गोथेनबर्ग के शोधकर्ताओं ने एक FPGA-त्वरित ग्राफ न्यूरल नेटवर्क डिकोडर बनाया जो <1μs विलंबता के साथ 1.47×10⁻⁵ त्रुटि दर प्राप्त करता है — जो दूरी 7 तक के सरफेस कोड के लिए MWPM से 13% बेहतर है।

#क्वांटमत्रुटिसुधार #FPGA #समाचार

FPGA-beschleunigter GNN-Decoder durchbricht den Geschwindigkeit-Genauigkeit-Kompromiss bei der Quantenfehlerkorrektur

Forscher der Chalmers- und Göteborger Universität entwickelten einen FPGA-beschleunigten Graph-Neuronales-Netz-Decoder, der eine Latenz von <1μs bei einer Fehlerrate von 1,47×10⁻⁵ erreicht — 13% besser als MWPM — für Oberflächencodes bis zur Distanz 7.

#Quantenfehlerkorrektur #FPGA #Neuigkeiten