Fabrication of silicon photonics with integrated III–V materials at scale The growing demand for high-bandwidth, energy-efficient optical transceivers has accelerated interest in heterogeneous integration of III–V semiconductors on silicon—pairing high...

www.laserfocusworld.com/optics/artic...
#photonics #silicon #interconnects #III-V

Fabrication of silicon photonics with integrated III–V materials at scale The growing demand for high-bandwidth, energy-efficient optical transceivers has accelerated interest in heterogeneous integration of III–V semiconductors on silicon—pairing high...

www.laserfocusworld.com/optics/artic...
#optics #silicon #photonics #interconnects #transceivers

An Explosion In Interconnect Complexity The chip industry has gone from two routing platforms to five. That's a lot.

For decades, electronics offered 2 levels of routing structure to manage signals that originate or terminate in an IC. Recently, that number has risen to 5, bringing greater complexity and design decisions
semiengineering.com/an-explosion...

#interconnects #semiconductor

Constraint Payments Soar to New Record As the Telegraph states, this is essentially a Scottish problem, as there is not enough transmission capacity to carry all the wind power south when it is windy. But naively, they then go on to say that OFGEM are spending £90 billion on grid upgrades to deal with this problem.

Interconnects and Passive Components Market Size, Share, and Industry Analysis: What to Expect by 2026 www.marketresearchfuture.com/reports/inte... #interconnects, #and, #passive, #components, #market, #size, #share, #industry, #analysis:, #what

Penguin Solutions SMART Modular CXL NV-CMM E3.S 2T Memory Module Achieves CXL Compliance Fremont, Calif.—January 14, 2026—Penguin Solutions, Inc. (Nasdaq: PENG) a provider of high-performance...

#HPC-AI #Hardware #Interconnect #Interconnects #News #CXL […]

[Original post on insidehpc.com]

Penguin Solutions SMART Modular CXL NV-CMM E3.S 2T Memory Module Achieves CXL Compliance Fremont, Calif.—January 14, 2026—Penguin Solutions, Inc. (Nasdaq: PENG) a provider of high-performance...

#HPC-AI #Hardware #Interconnect #Interconnects #News #CXL […]

[Original post on insidehpc.com]

Author: Lex Fridman Handle: lexfridman

Why does Amazon AWS keep winning? - clip from Lex Fridman Podcast with Dylan Patel and Nathan Lambert. Guest bio: Dylan Patel is the founder of SemiAnalysis, a research & analys #AWS #SemiAnalysis #Semiconductors #GPUs #CPUs #AI2 #Interconnects #Podcast

Future of the Fabric: #AI Factories Fuel Global Battle Over #Supercomputing #Interconnects

www.eetimes.com/ai-factories...

#HPC @eetimes.bsky.social

Original post on mindly.social

Subject: complaint about cargo-culting audiophools and the #marketers that exploit them

I saw a new #scam yesterday. Well, new to me. It's probably been around forever.

There are many, many #fraudulent products and ideas out there that target the self-described "audiophiles". And because such […]

Save the date! The next @ethernetalliance.bsky.social #HSNPlugfest is on the books for Dec 8–12, 2025 in Santa Clara, CA. We'll be testing #interoperability from #200G to #1.6TbE, #interconnects, and more. Get ready for next-gen #Ethernet speeds. Details: bit.ly/EA-HSNPlugfe... #VoiceOfEthernet

#GenAI is pushing computing beyond its limits, demanding new chips, faster #interconnects, and greater #energy innovation. It’s more than an evolution; it’s a full-system reboot. @venturebeat.com digs deeper here: bit.ly/4litCW6

(Pssst! At #TEF2025, we'll talk how #Ethernet meets #AI's challenges.)

AMD Licenses Arteris Network-on-Chip Interconnect IP CAMPBELL, Calif. – August 4, 2025 – Arteris, Inc. (Nasdaq: AIP), a provider of semiconductor system IP for accelerating system-on-chip (SoC)...

#Interconnects #News #AMD #Arteris #Network-on-Chip #NoC #interconnect

Origin | Interest | Match

New technical papers recently added to Semiconductor Engineering’s library
semiengineering.com/chip-industr...

#semiconductor #analog #interconnects #photonics #GPU

Miniaturization Trend Driven by Transition to High-Density Interconnects Embedded systems and their components have steadily gotten smaller throughout the industry’s history. While miniaturization itself may be nothing new, it’s reaching new heights, thanks in equal part to growing demands and the rise of technologies enabling further shrinkage. High-density interconnects (HDIs) are among the most impactful of these innovations. HDIs have been around for some time now, but manufacturers have only recently begun to capitalize on their full potential.

Recognizing the importance of high-density interconnects starts with understanding the modern demand for miniaturization. #Embedded #Interconnects

ACT Entertainment announces sales leadership updates Woody Woodard and Preston Clark assume vice director roles for interconnects and accessories sales teams The post ACT Entertainment announces sales leadership updates appeared first on Installation.

PODCAST: Interview with Jeff Hutchins, Ranovus and OIF Episode 57 of Following the Photons: A Photonics Podcast features Jeff Hutchins, director of optical technologies in the CTO office at Ranovus and treasurer of the Optical Internetworki...

www.laserfocusworld.com/podcasts/pod...
#optics #interconnects #photonics @jmurphoton.bsky.social

Intel Upgrades Chip Packaging for Bigger AI This week at the IEEE Electronic Components and Packaging Technology Conference, Intel unveiled that it is developing new chip packaging technology that will allow for bigger processors for AI. With Moore’s Law slowing down, makers of advanced GPUs and other data center chips are having to add more silicon area to their products to keep up with the relentless rise of AI’s computing needs. But the maximum size of a single silicon chip is fixed at around 800 square millimeters (with one exception), so they’ve had to turn to advanced packaging technologies that integrate multiple pieces of silicon in a way that lets them act like a single chip. Three of the innovations Intel unveiled at ECTC were aimed at tackling limitations in just how much silicon you can squeeze into a single package and how big that package can be. They include improvements to the technology Intel uses to link adjacent silicon dies together, a more accurate method for bonding silicon to the package substrate, and system to expand the size of a critical part of the package that remove heat. Together, the technologies enable the integration of more than 10,000 square millimeters of silicon within a package that can be bigger than 21,000 mm2—a massive area about the size of four and a half credit cards. ## EMIB gets a 3D upgrade One of the limitations on how much silicon can fit in a single package has to do with connecting a large number of silicon dies at their edges. Using an organic polymer package substrate to interconnect the silicon dies is the most affordable option, but a silicon substrate allows you to make more dense connections at these edges. Intel’s solution, introduced more than five years ago, is to embed a small sliver of silicon in the organic package beneath the adjoining edges of the silicon dies. That sliver of silicon, called EMIB, is etched with fine interconnects that increase the density of connections beyond what the organic substrate can handle. At ECTC, Intel unveiled the latest twist on the EMIB technology, called EMIB-T. In addition to the usual fine horizontal interconnects, EMIB-T provides relatively thick vertical copper connections called through-silicon vias, or TSVs. The TSVs allow power from the circuit-board below to directly connect to the chips above instead of having to route around the EMIB, reducing power lost by a longer journey. Additionally, EMIB-T contains a copper grid that acts as a ground plane to reduce noise in the power delivered due to process cores and other circuits suddenly ramping up their workloads. “It sounds simple, but this is a technology that brings a lot of capability to us,” says Rahul Manepalli, vice president of substrate packaging technology at Intel. With it and the other technologies Intel described, a customer could connect silicon equivalent to more than 12 full size silicon dies—10,000 square millimeters of silicon—in a single package using 38 or more EMIB-T bridges. ## Thermal control Another technology Intel reported at ECTC that helps increase the size of packages is low-thermal-gradient thermal compression bonding. It’s a variant of the technology used today to attach silicon dies to organic substrates. Micrometer-scale bumps of solder are positioned on the substrate where they will connect to a silicon die. The die is then heated and pressed onto the microbumps, melting them and connecting the package’s interconnects to the silicon’s. Because the silicon and the substrate expand at different rates when heated, engineers have to limit the inter-bump distance, or pitch. Additionally, the expansion difference makes it difficult to reliably make very large substrates full of lots of silicon dies, which is the direction AI processors need to go. The new Intel tech makes the thermal expansion mismatch more predictable and manageable, says Manepalli. The result is that very-large substrates can be populated with dies. Alternatively, the same technology can be used to increase the density of connections to EMIB down to about one every 25 micrometers. ## A flatter heat spreader These bigger silicon assemblages will generate even more heat than today’s systems. So it’s critical that the heat’s pathway out of the silicon isn’t obstructed. An integrated piece of metal called a heat spreader is key to that, but making one big enough for these large packages is difficult. The package substrate can warp and the metal heat spreader itself might not stay perfectly flat; so it might not touch the tops of the hot dies it’s supposed to be sucking the heat from. Intel’s solution was to assemble the integrated heat spreader in parts instead of as one piece. This allowed it to add extra stiffening components among other things to keep everything in flat and in place. “Keeping it flat at higher temperatures is a big benefit for reliability and yield,” says Manepalli. Intel says the technologies are still in the in R&D stage and would not comment on when these technologies would debut commercially. However, they will likely have to arrive in the next few years for the Intel Foundry to compete with TSMC’s planned packaging expansion.

#AI #datacenters depend on high-speed #interconnects and connectors like #PCIe, #NVLink, and #InfiniBand, so where does Ethernet fit in?

As demands grow, #Ethernet’s evolving role in high-performance compute deserves a closer look. Explore the full article now at #EEWorldOnline: bit.ly/3FzjTvz

Die-to-die Interconnect Standards In Flux Many features of UCIe 2.0 seen as “heavy” are optional, causing confusion.

UCIe, a standard for die-to-die interconnect in advanced packages, has drawn concern about being too heavyweight with its 2.0 release.
semiengineering.com/die-to-die-i...

#UCIe #chiplets #semiconductor #interconnects

Our Spring 2025 issue of Quantum Innovators:
img.laserfocusworld.com/files/base/e...
#quantum #topology #interconnects #holograms

‘Photon-shuttling’ quantum interconnects enable remote entanglement In this Q&A with Aziza Almanakly, an electrical engineering and computer science graduate student within the Engineering Quantum Systems group of the Research Laboratory of Electronics...

www.laserfocusworld.com/quantum/arti...
#quantum #interconnects

🔥 One of the hottest topics at #OFC25 is getting a deeper dive next week. Join us for OIF’s 448Gbps Signaling for AI Workshop in Santa Clara next week, April 15–16.

🔗 www.oiforum.com/meetings-eve...

#OIF #AI #Networking #448Gbps #Hyperscale #ML #Interconnects #Datacenter

🚀 Join OIF’s workshop: “Addressing the Next Rate Challenges: 448Gbps Signaling for AI”

📅 April 15-16
🔗 Register: www.oiforum.com/aro/meeting/...

Co-sponsored by @ethernetalliance.bsky.social, OCP, @SNIA, @ultraethernet.bsky.social, & UALink Consortium.

#OIF #AI #448Gbps #Interconnects

A Federal "Take Over" of D.C.?
Learn how it #Interconnects to so much more...
Film Screening and Talk with
Producer Anna Reid Jhirad
Activist Anne Anderson
Tonight! Tuesday, February 25

7:30pmET • 6:30pmCT • 5:30pmMT • 4:30pmPT
bit.ly/Last-Battlefront
@uua.org @allsoulsunitarian.bsky.social

Save the date! The #OIF 448Gbps Signaling for #AI Workshop is happening April 15-16, 2025, in Santa Clara, CA. Co-sponsored by @ethernetalliance.bsky.social, this event will tackle next-generation challenges of high-speed #interconnects. Learn more now at: bit.ly/448GbpsSigna... #Ethernet #signaling

»#Intel looks beyond silicon, outlines breakthroughs in atomically-thin #2Dtransistors, #chippackaging, and #interconnects at IEDM 2024.«…