Chip Industry Week In Review From shoes to GPUs; super agents; TSMC, ASML results; new chiplets and test facilities; Stanford AI index; photonics deals; compute architecture hall of fame; teens for chips; AI security; automotive ...

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Why More CPUs Are Needed In Data Centers YouTube video by Semiconductor Engineering

General-purpose processing demands will multiply once machines are talking to machines.
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Untrusted Analog Components Add Risks For Critical Infrastructure A certificate-based, tamper-proof system can stifle growing grey-market and counterfeit problems. But it requires investment and a lot more coordination.

Rising concern over the source and destination of chips, and the components within them, is driving a global effort to tag them in a way that is permanent, immutable, and unclonable.
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Fast Isn’t Fast Enough: Redefining Metrics for Edge AI Why latency guarantees, memory movement, power budgets, and rapid model deployment now matter more than raw TOPS.

Today’s chip architect must contend with multiple factors when architecting AI processors for fast and efficient performance set against the context of rapidly evolving AI models. Part 1 of SE's most recent roundtable of experts.
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#EdgeAI

Startup Funding: Q1 2026 Massive rounds for AI, EDA, and manufacturing; 80 startups raise $8.4B.

Chip Industry's Quarterly Startup Funding Report
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#semiconductor #startups #funding

An Engineering Roadmap Toward Completely Neural Computers (Meta AI, KAUST) A new technical paper, “Neural Computers,” was published by researchers at Meta AI and KAUST. Abstract “We propose a new frontier: Neural Computers (NCs) — an emerging machine form that unifies comput...

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A New Era For Co-Processing Processor architectures are evolving faster than ever, but they still lag the pace of AI development. Chip architects must predict what will be required tomorrow in designs today.

New processor architectures are rapidly evolving thanks to changing workloads associated with AI, but no one processor can do it all. Coordination is easy on paper, but a lot more difficult in practice.

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What's Failing At The Interface In advanced packages, the interface is where problems show up, but rarely where they begin.

When something fails in advanced packaging, the interface is usually the first suspect.
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#semiconductor #advancedpackaging

AI Accelerators Usher In New Era For IC Test The number and variety of test interfaces, coupled with increased packaging complexity, are adding a slew of new challenges.

Special Report: Testing AI systems is a whole new ball game.
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#semiconductor #AI #AIAccelerators #HBM

Chip Industry Week In Review Tighter restrictions on DUV litho; Arm-IBM dual-architecture deal; power device trio; Intel takes full control of Irish fab; 1.4nm AI chip; data center heat islands; 300mm fab equipment spending; 67k ...

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#semiconductor #2nm #1nm #HBF #lithography

The One Bit Problem That Can Break a System Whether caused by cosmic radiation, voltage glitches, or adversarial attacks, bit flips threaten data integrity, safety critical operation, and the foundations of hardware security.

The flip of a tiny bit can bring down even the best-architected and most secure systems of systems, and despite decades of awareness, there still is no easy way to stop it.
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#semiconductor #bitflip

AI's Potential And Limitations In Chip Design Full automation is still a goal, but humans will still be in the loop for the foreseeable future.

Opportunities and challenges of using AI in chip design. Interesting panel discussion with experts from Intel, Synopsys, AMD, Nvidia, Microsoft, and UC Berkeley
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#AI #chipdesign #EDA

Designing, developing, and manufacturing chips at 2nm and below requires a whole new set of business and technology tradeoffs that are dramatically more impactful at every turn, from architectural inception to manufacturing yield.
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#2nm #semiconductor

New technical papers recently added to Semiconductor Engineering’s library
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Chip Industry Week In Review Arm's game-changer; QC breaks in 2029; lawsuits on 11 GF patents; new fabs; helium atom beam litho; AI tool funding; 90% less GenAI cost; 2D materials roadmap; Intel's security report.

Catch up on the latest news in the semiconductor industry semiengineering.com/chip-industr...

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Memory Wall Gets Higher With SRAM failing to scale in recent process nodes, the industry must assess its impact on all forms of computing. There are no easy solutions on the horizon.

If fast memory becomes the limiter to compute, then compute must start to use the available memory more efficiently.
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#SRAM

Beating The Heat In 3D Packages Thermal management is the biggest performance and reliability bottleneck in multi-die assemblies.

Semiconductor Engineering's latest special report out today semiengineering.com/beating-the-...

#semiconductor #thermalmanagement #3DIC #warpage #CTE #STCO #thermalmodeling

Chip Industry Week In Review HBM4 deal; war's impact on supply chain; U.S. AI framework; GPU smuggling; restart of H200 processors for China; SK hynix's memory prediction; TFLN photonics deal; test and metrology platforms; NoC ve...

Never a dull moment in the chip industry semiengineering.com/chip-industr...

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Advanced Packaging Limits Come Into Focus Mechanical and process control limits are now shaping what can be manufactured at scale.

Insights from this year’s iMAPS conference semiengineering.com/advanced-pac...
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Memory For AI At The Edge Why new LPDDR releases make them the memories of choice for many applications.

Steve Woo, Rambus fellow & distinguished inventor, talks about different DRAM options, why the latest LPDDR versions are garnering so much attention on the edge, how they compare with other types of DRAM, & how it can be packaged to provide more capacity.
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Scale-Up, Scale-Out Get a New Partner For reaching farther into another data center, developers are now talking about scale-across.

If more uncommitted resources are needed than are available in the data center, scale-across is the new buzzword for reaching farther into another data center.
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#datacenter

AI Power on the Edge Architecting solutions for edge AI is not about minimizing cloud solutions or making small extensions of existing MCUs/MPUs. It's a hardware/software/model co-development problem.

Implementing AI on the edge is driven by a different set of metrics than training or even inference in the cloud. It makes power a first-class citizen, if not the most important design consideration, and it cannot be done successfully without co-design.
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New technical papers recently added to Semiconductor Engineering’s library
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Chip Industry Week In Review Preparing for sub-1nm; Iran war fallout on chips; Embedded World announcements; ramping Japan; foundry rankings; MIPI PHY IP; clocking tech; cybersecurity policy; imec's new consortium; neuromorphic c...

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CPO Is Extending The Limits Of What's Possible In AI Data Centers Co-packaged optics technology will have a big impact on system power and the cost of data movement.

Special Report: For the chip architects and engineers, there are many aspects to CPO.
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#CPO #AIdatacenters

Detecting Chemical Variability At Advanced Nodes Yield loss is increasingly molecular in origin and invisible to conventional inspection.

As semiconductor manufacturing pushes toward angstrom-scale devices and heterogeneous integration, the nature of defects affecting yield and reliability is changing.
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#semiconductor #yield

Digital Twins: The Cloud's The Limit Chip industry leverages massive compute resources and AI for virtual sandboxes.

Digital twin technology is drawing significant attention across the chip industry, even though it’s still unclear who will own or manage them, what the optimal levels of abstraction will be, and how they will be connected.
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Tool Matching Getting Tougher Across Test & Metrology:
New techniques are needed to keep pace with ever-shrinking features and tolerances.
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Limiting AI/ML Tools To Ensure Physical AI Safety, Security Tools designed to verify and monitor physical AI systems offer value, but human oversight is needed to prevent accidents and unexpected behavior.

Limiting AI/ML Tools To Ensure Physical AI Safety, Security
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#physicalAI #cybersecurity #LLMs