* support negative numbers in strd_int * optimise strd_int, reducing branches in loop from 3 to 1 * reject invalid hex characters in strx_int :;<=>? (U+003A-0x003F) * add number/string example program software/book/ch06/num_str.s * rename keyboard include to unicode and change constants UNI_ -> UCS_ * add chapter 6 memory map to README

I've just updated 🏝️Isle chapter 6 software. It's exciting to work on big designs and graphics engines, but building a usable computer is about the small things too. #FPGAFriday

github.com/projf/isle/t...

ULX3S FPGA dev board connected to monitor showing number guessing game.

Board testing in advance of #FPGAFriday. The answer was 42. #ULX3S

Happy #FPGAFriday. I'm starting work on the next part of 🏝️Isle #FPGA Computer. I'm looking at input and the early system library. UTF-8 is surprisingly easy to decode in assembler; that's not some sort of humble brag, it's a testament to the design of UTF-8.

Happy #FPGAFriday. The hardware for the next installment of 🏝️ Isle #FPGA Computer is ready; now I'm working on docs, a new blog post, and an update for my sponsors. I'm aiming for a public update next Friday. [1/2]

No FPGA for me today 😢, so I'd appreciate hearing about your hardware projects. #FPGAFriday

Hello hardware friends, it's a hot #FPGAFriday on the south coast. I'm writing tests and docs today, which is surprisingly satisfying if it's for a project you care about.

What are you working on today?

ULX3S FPGA dev board connected via DVI to monitor. Monitor is displaying the letters A-O in blue in an angular geometric font.

Got time to add more letters on the train yesterday. Happy #FPGAFriday.

Recommended FPGA Sites This page collects some of my favourite FPGA resources from across the Internet. FPGA Learning Resources Black Mesa Labs FPGA Tutorial Bruno Levy’s Learn FPGA fpga4fun.com fpgacpu.ca Nandland Project ...

It's about time I updated my recommended #FPGA links. Send me a suggestion this #FPGAFriday. 😊 projectf.io/recommended-...

ECP5 FPGA Clock Generation Yosys and nextpnr have excellent support for Lattice ECP5 FPGAs. However, without using the ECP5 PLL (phase-locked loop), you’re stuck running at the speed of your dev board oscillator. This post outl...

Fearlessly generate your own clocks with Lattice ECP5 #FPGAs and Yosys. Includes worked examples for #ULX3S and easy to adapt to any dev board. Happy #FPGAFriday! @yosyshq.com projectf.io/posts/ecp5-f...