#Intel perfmon updated with #PantherLake
CPUID.1Ah.EAX values:
20000000 #Tremont
20000001 #Gracemont
20000002 #Crestmont
20000003 #Skymont
20000004 #Darkmont
40000000 #SunnyCove
40000001 #GoldenCove
40000002 #RedwoodCove
40000003 #LionCove
40000004 #CougarCove
github.com/intel/perfmo...
Interesting factors:
- #Goldencove has 3 load port (reason of the advantage over #CypressCove)
- zmm store readout is 7 vs 11+ clks on #AMD
- AMD Zens have just 10 register read port (mentioned in the optim. guide)
- 1 clk ternlog lat (2 clks on 2nd&3rd operand on AMD):
www.uops.info/html-lat/ZEN...
Always there is a faster code:
My current byte-histogram results vs 2024
It is interesting, that how closer is #Intel #GoldenCove to the theoretical limit (0.343 <-> 0.372) than #AMD #Zen5 (0.207 <-> 2.54)
x.com/InstLatX64/s...
#GFNI
Addendum: There is no port or throughput change here, 1|.5 P06 will be 3|.5 P06 (and 1|1 P1 -> 3|1 P1)
#Intel, #GoldenCove, #RaptorCove, #RedwoodCove
I could reproduce the phenomenon with only 14 instructions on #Intel #GoldenCove, #RaptorCove, #RedwoodCove. It appears only with the 64b-immediate initialization of the 2nd (3rd) operand in the -1024<=imm32<=1023 range.
On #LionCove... 1/2
Unaffected #Intel cores:
#CypressCove in #RocketLake
#WillowCove in #TigerLake
#Gracemont in #AlderLake & #RaptorLake
#Crestmont in #MeteorLake
#Skymont in #ArrowLake
Affected cores:
#GoldenCove in #AlderLake
#RaptorCove in #RaptorLake
#RedwoodCove in #MeteorLake
#LionCove in #ArrowLake
New dumps:
- #Intel Core i3-1220P ( #AlderLakeP) 906A4 #GoldenCove + #Gracemont x64 InstLat dump
GitHub:
github.com/InstLatx64/I...
#Intel
- Core Ultra 7 155H #MeteorLakeU A06A4 #RedwoodCove, #Crestmont
- Core i9-13900K #RaptorLakeS B0671 #RaptorCove, #Gracemont
- Core i9-12900K #AlderLakeS 90672 #GoldenCove, #Gracemont (w/ +w/o #AVX512)
- Core i7-11900K #RocketLakeS A0671 #CypressCove
4/5
