My quick note about #Intel
#BartlettLake CPUID D0670
and
#RaptorLake CPUID B0671 #RaptorCove
instruction level differences

This is a bit surprising, all #Intel #Xeon6 63xxP SKUs are #RaptorCove based, LGA1700:

Addendum: There is no port or throughput change here, 1|.5 P06 will be 3|.5 P06 (and 1|1 P1 -> 3|1 P1)
#Intel, #GoldenCove, #RaptorCove, #RedwoodCove

I could reproduce the phenomenon with only 14 instructions on #Intel #GoldenCove, #RaptorCove, #RedwoodCove. It appears only with the 64b-immediate initialization of the 2nd (3rd) operand in the -1024<=imm32<=1023 range.

On #LionCove... 1/2

Unaffected #Intel cores:
#CypressCove in #RocketLake
#WillowCove in #TigerLake
#Gracemont in #AlderLake & #RaptorLake
#Crestmont in #MeteorLake
#Skymont in #ArrowLake

Affected cores:
#GoldenCove in #AlderLake
#RaptorCove in #RaptorLake
#RedwoodCove in #MeteorLake
#LionCove in #ArrowLake

#Intel
- Core Ultra 7 155H #MeteorLakeU A06A4 #RedwoodCove, #Crestmont
- Core i9-13900K #RaptorLakeS B0671 #RaptorCove, #Gracemont
- Core i9-12900K #AlderLakeS 90672 #GoldenCove, #Gracemont (w/ +w/o #AVX512)
- Core i7-11900K #RocketLakeS A0671 #CypressCove
4/5