Adding an enable signal to 🏝️ Isle.Computer drawing engine was more of a pain than I expected, but we're now ready to share vram access with the CPU. On the plus side, this also allows you to slow the action down so you can see the drawing happen. #FPGA #verilog
A Rust compiler builds a working RISC-V CPU in Factorio! This wild project exposes the hidden "abstraction cost" and physical realities of hardware design. Mind-blowing engineering!
thepixelspulse.com/posts/verilog-factorio-c...
#verilog #factorio #riscv
Fun in the frequency domain 🤓 Camera pointed at it's own display also showing audio FFT for cool glitchy visualizer effect. Video processing all done in PipelineC hardware. And how?
github.com/JulianKemmer...
#hardware #fpga #dsp #rtl #hdl #hls #verilog #vhdl #pipelinec
SystemLisp - an HDL simulator written in Common Lisp
https://github.com/systemlisp
#lisp #commonlisp #hdl #rtl #verilog #design #verification #vhdl #systemverilog #vlsi #programming #fpga
Then something for the #Verilog and #Factorio crowd to bond over: a tool for taking a Verilog chip design and putting into the game... as a functional factory.
Demos of its capabilities go all the way up to a 32-bit #RISCV CPU […]
system diagram of software and hardware
@nlnetlabs.bsky.social NLnet Foundation funded open source WireGuard router in FPGA. Featuring PipelineC for cryptography blocks 🤓
github.com/JulianKemmer...
#hardware #fpga #rtl #hdl #hls #verilog #vhdl #cryptography #wireguard #pipelinec
latchup throughput ranking table and logo
PipelineC holds the throughput lead on Latchup.app. For now! How does your design stack up against a pipelining tool? Far too time consuming and fun of a site 🤓 Look forward to seeing competing solutions.
github.com/JulianKemmer...
#fpga #asic #rtl #hdl #verilog #vhdl #hls #eda
aof banner
Check out PipelineC #HDL Advent of FPGA #hardware solutions: high perf, deeply pipelined, multiple #FPGA platforms, 10's Gbit per sec throughput, easily scales: variable latency off chip mem, faster off chip IO and more resources.
github.com/JulianKemmer...
#rtl #hls #verilog #vhdl #asic #eda
Bubble Universe implemented as a #Verilog #FPGA core for the #MiSTer platform. Here demonstrated on a #Heber #MiSTer #multisystem2
Download and source in the video description.
www.youtube.com/watch?v=2IeP...
@heber-limited.bsky.social @multisystemfpga.bsky.social @retrocollective.co.uk
Advent of Code Day 5: Iterates over RAM holding fresh ID ranges. Autopipeline checks N IDs against M ranges each cycle. Easily does N=3,M=2 at ~235MHz, ~1.4 billion ID-in-range checks computed per sec 😎
github.com/JulianKemmer...
#aoc25 #fpga #hardware #verilog #vhdl #hdl #rtl #hls #asic #eda
My #Verilog Language Syntax Highlighter for Visual Studio can also be found at the Marketplace:
marketplace.visualstudio.com/items?itemNa...
Screen snip of Visual Studio with the VerilogLanguage install screen
Hello all my #FPGA friends that also use Visual Studio!
I've updated my #Verilog Syntax Highlighter to work with VS2022 and VS2026.
Extensions - Manage Extensions - Browse
Type: Verilog
then click Install.
Please take it for a test drive and let me know what you think.
Advent of Code Day 7: very simple design, good intro to #pipelinec. processing all ~hundreds of elements of an entire line each cycle. ~600 million to ~5.3 billion tachyon beams splitting per second. 😎
github.com/JulianKemmer...
#aoc25 #fpga #hardware #verilog #vhdl #hdl #rtl #hls #asic #eda
I've accidentally started reading about flood fill algorithms. Span filling looks doable in a reasonable amount of logic and memory (for non-pathological shapes). I'm almost tempted to give it a go in #Verilog over Christmas.🎄
Advent of Code 2025 Day 2 in FPGA 🤓
github.com/JulianKemmer...
#fpga #hardware #verilog #vhdl #hdl #rtl #hls #asic #eda
...se conectan al microcontrolador SAM D21! 💾⚙️
Ahora viene la parte divertida: ejecutar el Fitter (Colocación y Ruta) para mapear de verdad esta lógica compleja en los diminutos recursos del chip Cyclone 10 LP. ¡Deséame suerte para que el encaje sea exitoso!
#FPGA #Verilog #HardwareDesign
Author: Furt_Tech Industries Handle: furt_tech
FPGA is PAIN. #programming #electronicsprojects #verilog #fpga #meme #tiktok #archive
VerilogMonkey Shows Parallel Scaling Boosts LLM-Generated Hardware Code
VerilogMonkey shows that generating hundreds of Verilog snippets in parallel boosts LLM performance on hardware code benchmarks, achieving better results without extra model tuning. getnews.me/verilogmonkey-shows-para... #verilog #llm #parallel
HarvOS Logo
HarvOS is a research concept for a secure OS and processor design. It introduces a novel combination of Harvard separation, MMU, and MPU, aiming to make entire classes of software exploits structurally impossible. (Work in progress)
github.com/decipher2k/H...
#processor #verilog #osh #security
EDA tool runtime too long? DashRTL is the ONLY solution that accelerates RTL analyze and elaborate with MULTI-CORE processing.
#VLSI #SystemVerilog #Verilog #RTL #HDL
"How do FPGAs execute blocking assignments in one clock cycle?"
Is the perfect question to frame common learning curve hurdles that folks need to get over when learning HDL.
www.reddit.com/r/FPGA/comme...
#fpga #hardware #verilog #vhdl #hdl #rtl #hls #asic #eda
Защитим вдов и сирот от хищных ИИ-стартаперов Ко мне на днях обратились сначала два стартапера, а потом и из ...
#SystemVerilog #Verilog #Electronic #Design #Automation #ChatGPT #Claude #deepseek #anthropic #AI #EDA
Origin | Interest | Match
Защитим вдов и сирот от хищных ИИ-стартаперов Ко мне на днях обратились сначала два стартапера, а потом и из ...
#AI #Anthropic #chatgpt #claude #deepseek #Electronic #Design #Automation #ml #SystemVerilog #Verilog
Origin | Interest | Match
#C #Programming #Electrical #Engineering #Electronics #Microcontroller #Verilog #/ #VHDL
Origin | Interest | Match
