Fun in the frequency domain 🤓 Camera pointed at it's own display also showing audio FFT for cool glitchy visualizer effect. Video processing all done in PipelineC hardware. And how?

github.com/JulianKemmer...

#hardware #fpga #dsp #rtl #hdl #hls #verilog #vhdl #pipelinec

systemlisp - Overview An experimental HDL simulator written in Common Lisp focused on interactive and extensible hardware design and verification. - systemlisp

SystemLisp - an HDL simulator written in Common Lisp

https://github.com/systemlisp

#lisp #commonlisp #hdl #rtl #verilog #design #verification #vhdl #systemverilog #vlsi #programming #fpga

system diagram of software and hardware

@nlnetlabs.bsky.social NLnet Foundation funded open source WireGuard router in FPGA. Featuring PipelineC for cryptography blocks 🤓

github.com/JulianKemmer...

#hardware #fpga #rtl #hdl #hls #verilog #vhdl #cryptography #wireguard #pipelinec

latchup throughput ranking table and logo

PipelineC holds the throughput lead on Latchup.app. For now! How does your design stack up against a pipelining tool? Far too time consuming and fun of a site 🤓 Look forward to seeing competing solutions.

github.com/JulianKemmer...

#fpga #asic #rtl #hdl #verilog #vhdl #hls #eda

Now scale that to real-time image processing on a satellite or surveillance drone. You're doing millions of these operations per second. The power budget? Maybe 5-10 watts. The weight budget? Every gram matters when you're fighting gravity or extending flight time.

Just shipped a write-up on my latest weekend project: Optimizing 3x3 Convolutions for FPGAs. 🛠️

By constraining the weights to Powers-of-Two (PoT), I managed to replace 33% of Muls.

Curious to hear what the hardware folks think:
www.dockerr.blog/blog/lowrank...

#FPGA #VHDL #Embedded #SpaceTech

aof banner

Check out PipelineC #HDL Advent of FPGA #hardware solutions: high perf, deeply pipelined, multiple #FPGA platforms, 10's Gbit per sec throughput, easily scales: variable latency off chip mem, faster off chip IO and more resources.

github.com/JulianKemmer...

#rtl #hls #verilog #vhdl #asic #eda

--- Results --- Correctness: PASSED Software Time: 3310 us Hardware Time: 14588 us Speedup: 0.2269x

Hardware Decelerator #FPGA #SoC #PolarFire #VHDL #AXI

Shelf full of computing and computer science books.

The collection grows!

You want the full list? 300 characters is pitiful and there's not enough space in the Alt text. So, here we go... 🧵

#shelfie #golang #compilers #pascal #programming #programmingbooks #retrocomputing #vhdl #psion

A very simple MIPS processor I've built as part of a university lecture running on my Icepi Zero! #FPGA #VHDL #DVI #MIPS #processor #hardware-development

An Icepi Zero (FPGA development board in the form factor of a Rasberry Pi Zero) with plugged in mini HDMI and USB-C cables in front of a monitor showing the text "HELLO WORLD! :3" in a square, monospaced, wonky-looking, self-made font.

Hello World from my new Icepi Zero! :D #FPGA #Lattice #VHDL #DVI

Advent of Code Day 5: Iterates over RAM holding fresh ID ranges. Autopipeline checks N IDs against M ranges each cycle. Easily does N=3,M=2 at ~235MHz, ~1.4 billion ID-in-range checks computed per sec 😎

github.com/JulianKemmer...

#aoc25 #fpga #hardware #verilog #vhdl #hdl #rtl #hls #asic #eda

Advent of Code Day 7: very simple design, good intro to #pipelinec. processing all ~hundreds of elements of an entire line each cycle. ~600 million to ~5.3 billion tachyon beams splitting per second. 😎

github.com/JulianKemmer...

#aoc25 #fpga #hardware #verilog #vhdl #hdl #rtl #hls #asic #eda

Advent of Code 2025 Day 2 in FPGA 🤓

github.com/JulianKemmer...

#fpga #hardware #verilog #vhdl #hdl #rtl #hls #asic #eda

August Technical Puzzle Hint — PART 2: THE INVESTIGATION — VHDL Testbench to expose the Costas Loop Error Starvation — — This testbench will demonstrate the intermittent lock loss — and help us discover the root cause through systematic — investigation. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; use IEEE.MATH_REAL.ALL; use STD.TEXTIO.ALL; use IEEE.STD_LOGIC_TEXTIO.ALL; entity tb_costas_mystery is end entity; architecture … Continue reading "August Technical Puzzle Hint"

August Technical Puzzle August Puzzle: The Mysterious Lock Loss — SCENARIO: You’re debugging a Costas loop implementation that works — perfectly in simulation but fails intermittently in hardware. — The loop locks quickly to F1 (carrier + 1kHz), but when the — input switches to F2 (carrier + 3kHz), it sometimes loses lock — entirely instead of reacquiring. … Continue reading "August Technical Puzzle"

August Technical Puzzle August Puzzle: The Mysterious Lock Loss — SCENARIO: You’re debugging a Costas loop implementation that works — perfectly in simulation but fails intermittently in hardware. — The loop locks quickly to F1 (carrier + 1kHz), but when the — input switches to F2 (carrier + 3kHz), it sometimes loses lock — entirely instead of reacquiring. … Continue reading "August Technical Puzzle"

August Technical Puzzle August Puzzle: The Mysterious Lock Loss — SCENARIO: You’re debugging a Costas loop implementation that works — perfectly in simulation but fails intermittently in hardware. — The loop locks quickly to F1 (carrier + 1kHz), but when the — input switches to F2 (carrier + 3kHz), it sometimes loses lock — entirely instead of reacquiring. … Continue reading "August Technical Puzzle"

August Technical Puzzle August Puzzle: The Mysterious Lock Loss — SCENARIO: You’re debugging a Costas loop implementation that works — perfectly in simulation but fails intermittently in hardware. — The loop locks quickly to F1 (carrier + 1kHz), but when the — input switches to F2 (carrier + 3kHz), it sometimes loses lock — entirely instead of reacquiring. … Continue reading "August Technical Puzzle"

Software, FPGA Execution, a PipelineC response

"How do FPGAs execute blocking assignments in one clock cycle?"

Is the perfect question to frame common learning curve hurdles that folks need to get over when learning HDL.

www.reddit.com/r/FPGA/comme...

#fpga #hardware #verilog #vhdl #hdl #rtl #hls #asic #eda

Energy-Efficient Fan Control Algorithm Development Electronics & C Programming Projects for €30-250 EUR. I'm seeking an experienced developer to design a control algorithm for a 3-phase permanent magnet synchronous motor

#C #Programming #Electrical #Engineering #Electronics #Microcontroller #Verilog #/ #VHDL
Origin | Interest | Match

MEGA65 Audio Amp Fix: Solving the R3 Internal Speaker Issue - The Oasis BBS Learn how Gurce fixed the MEGA65 R3's audio amp, including troubleshooting, solutions, and a demo of the internal speakers in action.

MEGA65 Audio Amp Fix: Solving the R3 Internal Speaker Issue
#MEGA65 #AudioAmplifier #TechFix #RetroComputing #VHDL #Troubleshooting #InternalSpeakers #SSM2518Amp

theoasisbbs.com/mega65-audio...

circuit design Electronics & Engineering Projects for $30-250 USD. I have a simple circuit diagram and would like to add reverse polarity protection to ensure the components remain safe

www.freelancer.com/projects/electrical-engi...

#Circuit #Design #Electrical #Engineering #Electronics #Engineering #Verilog #/ #VHDL

Result Details

The Spade Hardware Description Language Spade is an open-source hardware description language (HDL) developed at Linköping University, Sweden. Other HDLs you might have heard of include Verilog and VHDL. Hardware engineers use HDLs to define …read more

Bitbucket

VHDL for LBM D1Q3 semi-stable node! Fixed-point, BGK collision w/ stability control. Great for hardware acceleration of fluid dynamics! #VHDL #LBM #FPGA
The theory is still being proven but I will make it public↓
bitbucket.org/oreno-ie/zar...

Bitbucket

Open-source VHDL implementation of the Lattice Boltzmann Method (LBM) with fixed-point arithmetic. Optimized for FPGA simulation & hardware acceleration. 🚀　#HPC #VHDL #FPGA #LBM
bitbucket.org/oreno-ie/lbm...
This is just a preprint of the theory so far.
zenodo.org/records/1509...

Why do you use #verilog versus #VHDL versus #Systemverilog ?
I learned VHDL first on an #altera DE0-Nano as a hobby. then formally learn verilog on the realdigital blackboard( Xilinx Zynq SoC ) and now professionally program on #Xilinx Zynq ultrascale+ MPSoC.