Fun in the frequency domain 🤓 Camera pointed at it's own display also showing audio FFT for cool glitchy visualizer effect. Video processing all done in PipelineC hardware. And how?
github.com/JulianKemmer...
#hardware #fpga #dsp #rtl #hdl #hls #verilog #vhdl #pipelinec
SystemLisp - an HDL simulator written in Common Lisp
https://github.com/systemlisp
#lisp #commonlisp #hdl #rtl #verilog #design #verification #vhdl #systemverilog #vlsi #programming #fpga
And, always tell patients that we humans have 0 need to eat cholesterol. We synthesize it. We’re healthier when we eat exclusively plants & mushrooms 🌱🍄
… and may never need to worry about our LDL-c levels 😎
#ApoB #HeartDisease #cardiology #prevention #CVD #HDL #LDL #Cholesterol #diet #itsTheDiet
system diagram of software and hardware
@nlnetlabs.bsky.social NLnet Foundation funded open source WireGuard router in FPGA. Featuring PipelineC for cryptography blocks 🤓
github.com/JulianKemmer...
#hardware #fpga #rtl #hdl #hls #verilog #vhdl #cryptography #wireguard #pipelinec
latchup throughput ranking table and logo
PipelineC holds the throughput lead on Latchup.app. For now! How does your design stack up against a pipelining tool? Far too time consuming and fun of a site 🤓 Look forward to seeing competing solutions.
github.com/JulianKemmer...
#fpga #asic #rtl #hdl #verilog #vhdl #hls #eda
I am happy to announce that the @icepi-zero-bot.at.wafrn.jcm.re has Veryl support (it actually had it since a couple of days, but now I finally have a tiny bit of time to announce it)!
Thanks to @Tathar for the request and the help with setting things up. #FPGA #Icepi-Zero #fedibot #Veryl #HDL
✨Tiny good cholesterol heroes patrol our bodies, clearing artery-clogging debris! 🤯 But how are these vital protectors *made*? 🤔 #HDL 💖
Source: phys.org/news/2025-09-good-choles...
shared resource bus diagram
Existing libraries help: memory mapping is as simple as a struct. All stitched together with valid ready handshaking 'streams'. Writes done over StreamSoC's AXI-Lite like 'shared resource bus' that comes with helper FSMs
github.com/JulianKemmer...
#hardware #fpga #rtl #hls #hdl #graphics #gpu #cpu
Easy: draw_rect_t struct shared between embedded C software and PipelineC hardware. Mem mapped registers enqueue into command FIFO. Small hardware FSM reads from cmd FIFO does simple iteration to draw a rect of pixels.
github.com/JulianKemmer...
#hardware #fpga #rtl #hls #hdl #graphics #gpu #cpu
streamsoc new 2d drawing block
Is a hardware FSM that draws rectangles to a frame buffer a GPU? Well whatever you call it, it's no longer the CPU pushing pixels in the PipelineC StreamSoC design. Now it sends 'draw rectangle' commands to hardware. And how? #hardware #fpga #rtl #hls #hdl #graphics #gpu #cpu
aof banner
Check out PipelineC #HDL Advent of FPGA #hardware solutions: high perf, deeply pipelined, multiple #FPGA platforms, 10's Gbit per sec throughput, easily scales: variable latency off chip mem, faster off chip IO and more resources.
github.com/JulianKemmer...
#rtl #hls #verilog #vhdl #asic #eda
SALUD. Colesterol HDL y su relación con la salud cardiovascular. Este artículo trata sobre el colesterol HDL, qué es, cuáles son sus principales funciones, las últimas evidencias y qué lo diferencia del colesterol LDL www.cronicadelhenares.com/2026/01/salu... #colesterol #Salud #HDL #cardiovascular
「生きづらさ」を越えた創造性 岡山のデザインブランドHDLの挑戦 #HDL #人おこし #デザインブランド
岡山県発のデザインブランド「HDL（人おこしデザインラボ）」が一周年を迎え、生きづらさを抱えた若者に新たな就労の形を提供しています。クリエイターたちの作品も紹介！
生きづらさをデザインに変える岡山発HDLブランド、一周年を祝う #岡山県 #美作市 #HDL #山村エンタープライズ #人おこしデザインラボ
岡山県のデザインブランド「HDL」が一周年を迎え、若者たちの生きづらさを創造の力に変えています。支持が広がり、自己肯定感向上にも寄与しています。
New Program to Address Low HDL Levels Through Workplace Collaboration and Lifestyle Management #Japan #Tokyo #BODY_PALETTE #Fractal_Workout #HDL
企業向けHDLへのアプローチを示す新プログラムの開始 #東京都 #渋谷区 #健康経営 #HDL #フラクタルワークアウト
フラクタルワークアウトが新たに提供開始したHDL対策プログラムは、生活習慣改善を目指します。専門家が連携し、組織の健康経営を推進します。
Advent of Code Day 5: Iterates over RAM holding fresh ID ranges. Autopipeline checks N IDs against M ranges each cycle. Easily does N=3,M=2 at ~235MHz, ~1.4 billion ID-in-range checks computed per sec 😎
github.com/JulianKemmer...
#aoc25 #fpga #hardware #verilog #vhdl #hdl #rtl #hls #asic #eda
Advent of Code Day 7: very simple design, good intro to #pipelinec. processing all ~hundreds of elements of an entire line each cycle. ~600 million to ~5.3 billion tachyon beams splitting per second. 😎
github.com/JulianKemmer...
#aoc25 #fpga #hardware #verilog #vhdl #hdl #rtl #hls #asic #eda
#Abendessen #DtKüche Verachtet mir das Imbißmenü nicht.
#Wildschwein #Leberkäs vom #FleischerRex #AltesLand Dazu Bratkartoffeln & Gemüse aus #Hamburg Die Kartoffeln sind mit Schweinegriebenschmalz gebraten. Solange der #HDL -wert hoch ist, was bei mir der Fall ist, verzichte ich auf Schmalz nicht😋
📣 New Podcast! "The Buried Truth About High Cholesterol and Heart Disease" on @Spreaker #arteries #biology #cholesterol #diet #disease #fat #hdl #health #heart #inflammation #insulin #ldl #metabolism #nutrition #plaque #science #statins #sugar #triglycerides #wellness
Advent of Code Day 4: video-like stream of 'pixel' data to a sliding 3x3 window via line buffer fifos. Auto pipeline for kernel function (counting neighbors), ~150M windows per sec. github.com/JulianKemmer...
#fpga #rtl #hdl #hls #aoc25
Advent of Code Day 9: Iterates over RAM holding points. Autopipeline computes N rectangle areas per clock cycle and finds max. Easily does N=4 at ~100MHz with few pipeline stages, ~400M rect areas computed per sec 🎄
github.com/JulianKemmer...
#fpga #rtl #hdl #hls #aoc25
Advent of Code Day 3 pipelined no back pressure. N ascii chars as input each cycle. finding max pair of digits pipelined arbitrarily. 8 chars of input each cycle? no problem to get FMAX of 100+MHz.
~1 Gbyte per sec of ascii could be processed 😎 🎄
github.com/JulianKemmer... #aoc25 #fpga #hdl #hls
Ensuring Accuracy in LLM-Generated Hardware Logic Design Automation (IBM Research) A new technical paper “Mitigating hallucinations and omissions in LLMs for invertible problems: An application t...
#AI/ML/DL #Architectures #Design #& #Verification […]
[Original post on semiengineering.com]
Advent of Code 2025 Day 2 in FPGA 🤓
github.com/JulianKemmer...
#fpga #hardware #verilog #vhdl #hdl #rtl #hls #asic #eda
📣 New Podcast! "Colesterolo: la strategia in tre passi per riportarlo nella norma" on @Spreaker #alimentazionenaturale #benessere #colesterolo #hdl #ldl #prevenzione #salutedelcuore
#HDL Super Hi Reports Unaudited Financial Results for the Third Quarter of 2025
www.stocktitan.net/news/HDL/super-hi-report...
#Catheter-based #EndovascularDeNervation of the #celiac and #HepaticArteries safely improves glycemic control, boosts #HDL levels, and lowers blood pressure in patients with #Type2Diabetes, highlighting its potential as a novel therapy.
#OpenAccess in #STTT: doi.org/10.1038/s413...
