Fun in the frequency domain 🤓 Camera pointed at it's own display also showing audio FFT for cool glitchy visualizer effect. Video processing all done in PipelineC hardware. And how?
github.com/JulianKemmer...
#hardware #fpga #dsp #rtl #hdl #hls #verilog #vhdl #pipelinec
system diagram of software and hardware
@nlnetlabs.bsky.social NLnet Foundation funded open source WireGuard router in FPGA. Featuring PipelineC for cryptography blocks 🤓
github.com/JulianKemmer...
#hardware #fpga #rtl #hdl #hls #verilog #vhdl #cryptography #wireguard #pipelinec
Advent of Code Day 7: very simple design, good intro to #pipelinec. processing all ~hundreds of elements of an entire line each cycle. ~600 million to ~5.3 billion tachyon beams splitting per second. 😎
github.com/JulianKemmer...
#aoc25 #fpga #hardware #verilog #vhdl #hdl #rtl #hls #asic #eda
Check out @dutracgi@mastodon.radio 's very cool #16APSK #FPGA Modulator written in #PipelineC #HDL !
#dsp #sdr #rf #apsk #dac #deltasigma #space #qam #radio #hardware www.linkedin.com/pulse/16-aps...
Nice! Looking good 🤓
I like to take advantage of how 'C' can describe both software or custom hardware architectures 😏 #PipelineC . Sometimes you can even use the same code for a software renderer and hardware pipeline! And so many people know C, lets get them doing fun FPGA stuff!
Come on over to the Discord channel if you want to join the conversation about this fun work 🤓 discord.gg/vBUtmBZcxC #ice40 #FPGA #raspberrypi #pico-ice #PipelineC #HDL #Verilog #VHDL
Have been super pleased with the ice40 #FPGA and #raspberrypi board that pico-ice.tinyvision.ai sent me to experiment with. Many thanks and I look forward to putting together a talk for intro users getting started with #PipelineC and boards like the pico-ice 🤓 #HDL #Verilog #VHDL #hardware #embedded
Enjoying dreaming of a world better than #Verilog or #VHDL? Come chat over on the #PipelineC Discord 🤓
Trying to make #HDL #RTL easier to write. Folks with #embedded experience, ever written #C for a #microcontroller with #hardware in mind, should feel right at home in #FPGA discord.gg/Aupm3DDrK2
fft soc diagram cpu stages and memory map peripherals
Last week spoke at the first annual Soft #RISCV Systems Workshop 🔥 about a #hardware #SoC in #FPGA made using #PipelineC for doing #DSP computing #FFT with custom hardware. Can see slides here (no recording): docs.google.com/presentation... #RISC-V #eda #asic #hls #rtl #hdl #verilog #vhdl
Use #PipelineC to listen to FM #radio with an #FPGA #SDR! Huge thanks to @dutracgi@mastodon.radio and @Darkknight512 for making first version a great learning experience. And @deepwavedigital for the fantastic hardware platform and workplace <3
#hardware #hdl #hls #asic
github.com/JulianKemmer...
